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# pm_example2.c

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00081 #include "gpio.h"
    00082 #include "pm_at32ap7000.h"
    00083 #include "board.h"
    00084
    00085
    00088
    00089 #if BOARD == EVK1100
    00090 #  define EXAMPLE_GCLK_ID             0
    00091 #  define EXAMPLE_GCLK_PIN            AVR32_PM_GCLK_0_1_PIN
    00092 #  define EXAMPLE_GCLK_FUNCTION       AVR32_PM_GCLK_0_1_FUNCTION
    00093 // Note that gclk0_1 is pin 51 pb19 on AT32UC3A0512 QFP144.
    00094 #elif BOARD == EVK1101
    00095 #  define EXAMPLE_GCLK_ID             2
    00096 #  define EXAMPLE_GCLK_PIN            AVR32_PM_GCLK_2_PIN
    00097 #  define EXAMPLE_GCLK_FUNCTION       AVR32_PM_GCLK_2_FUNCTION
    00098 // Note that gclk_2 is pin 30 pa30 on AT32UC3B0256 QFP64.
    00099 #elif BOARD == STK1000
    00100 #  define EXAMPLE_GCLK_ID             0
    00101 #  define EXAMPLE_GCLK_PIN            AVR32_PM_GCLK_0_PIN
    00102 #  define EXAMPLE_GCLK_FUNCTION       AVR32_PM_GCLK_0_FUNCTION
    00103 #endif
    00104
    00105 #if !defined(EXAMPLE_GCLK_ID)  || \
    00106     !defined(EXAMPLE_GCLK_PIN) || \
    00107     !defined(EXAMPLE_GCLK_FUNCTION)
    00108 #  error The generic clock configuration to use in this example is missing.
    00109 #endif
    00111
    00112
    00113 /* Start PLL0, enable a generic clock with PLL0 output then switch main clock to PLL0 output.
    00114    All calculations in this function suppose that the Osc0 frequency is 12MHz. */
    00115 void local_start_pll0()
    00116 {
    00117   // Reset PM. Makes sure we get the expected clocking after a soft reset (e.g.: JTAG reset)
    00118   pm_reset();
    00119
    00120   // Start PLL0 giving 100 MHz clock
    00121   pm_pll_opt_t pm_pll_opt = {
    00122     .pll_id = 0,
    00123     .mul = 5,
    00124     .div = 1,
    00125     .osc_id = 0,
    00126     .count = 16,
    00127     .wait_for_lock = 1,
    00128   };
    00129   pm_start_pll(&pm_pll_opt);
    00130
    00131   // Divide HSB by 2, PBA by 4 and PBB by 2 to keep them below maximum ratings
    00132   pm_set_clock_domain_scaler(PM_HSB_DOMAIN, 2);
    00133   pm_set_clock_domain_scaler(PM_PBB_DOMAIN, 2);
    00134   pm_set_clock_domain_scaler(PM_PBA_DOMAIN, 4);
    00135
    00136   /* Setup generic clock on PLL0, with Osc0/PLL0, no divisor */
    00137   pm_gen_clk_opt_t pm_gen_clk_opt = {
    00138     .clock_source = PM_PLL0,
    00139     .divider = 0,
    00140   };
    00141   pm_start_generic_clock(EXAMPLE_GCLK_ID, &pm_gen_clk_opt);
    00142
    00143   /* Set the GCLOCK function to the GPIO pin */
    00144   gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
    00145
    00146   // Use PLL0 as clock source
    00147   pm_set_mclk_source(PM_PLL0);
    00148 }
    00149
    00150
    00151 /* \brief Software Delay
    00152  *
    00153  */
    00154 static void software_delay(void)
    00155 {
    00156   volatile int i;
    00157   for (i=0; i<1000000; i++);
    00158 }
    00159
    00160
    00161 /* \brief This is an example of how to configure and start a PLL from Osc0
    00162  * then configure the GCLK output to GLCK_0_1, and switch the main clock to
    00163  * PLL0 output.
    00164  *
    00165  */
    00166 int main(void)
    00167 {
    00168   /* start PLL0 and switch main clock to PLL0 output */
    00169   /* Also set-up a generic clock from PLL0 and output it to a gpio pin. */
    00170   local_start_pll0();
    00171
    00172   LED_Off(0xff);
    00173
    00174   /* Now toggle LED0 using a GPIO */
    00175   while(1)
    00176   {
    00177     LED_Toggle(LED0);
    00178     software_delay();
    00179   }
    00180 }