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# lcdc_testscreen_example.c

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00080 #include "usart.h"
    00081 #include "gpio.h"
    00082 #include "spi_at32ap7000.h"
    00083 #include "lcdc.h"
    00084 #include "board.h"
    00085 #include "ap7_utils.h"
    00086 #include <string.h>
    00087 #include "errno.h"
    00088 #include "print_funcs.h"
    00089 #include "ltv350qv.h"
    00090 #include "sdramc_at32ap7000.h"
    00091 #include "pm_at32ap7000.h"
    00092
    00093 extern void ltv350qv_power_on(volatile avr32_spi_t * spi, unsigned char chip_select);
    00094 extern int display_bm(lcdc_conf_t *lcdc_conf, void * bm_file);
    00095 extern void usdelay(unsigned long usec);
    00096 extern void usart_printHex(volatile avr32_usart_t * usart, const unsigned long n);
    00097 extern void usart_print(volatile avr32_usart_t * usart, char *str);
    00098
    00100 static lcdc_conf_t ltv350qv_conf = {
    00101   .dmabaddr1=0x10000000,
    00102   .dmabaddr2= 0,
    00103   .burst_length= 4,
    00104   .xres= 320,
    00105   .yres= 240,
    00106   .set2dmode= LCDC_MODE_2D_OFF,
    00107   .virtual_xres= 320,
    00108   .virtual_yres= 240,
    00109   .frame_rate= 75,
    00110   .lcdcclock= 40000000,
    00111   .guard_time= 2,
    00112   .memor= LCDC_BIG_ENDIAN,
    00113   .ifwidth= 0,
    00114   .scanmod= LCDC_SINGLE_SCAN,
    00115   .distype= LCDC_TFT,
    00116   .invvd= LCDC_INVERTED,
    00117   .invframe= LCDC_INVERTED,
    00118   .invline= LCDC_INVERTED,
    00119   .invclk= LCDC_INVERTED,
    00120   .invdval= LCDC_INVERTED,
    00121   .clkmod= LCDC_ALWAYS_ACTIVE,
    00122   .pixelsize= LCDC_BPP_24,
    00123   .ctrstval= 0x0f,
    00124   .ctrst_ena= LCDC_ENABLED,
    00125   .ctrst_pol= LCDC_NORMAL,
    00126   .ctrst_ps= LCDC_PRE_HALF,
    00127   .mval= 0,
    00128   .mmode= LCDC_EACH_FRAME,
    00129   .hpw= 16,
    00130   .hbp= 15,
    00131   .hfp= 33,
    00132   .vpw= 1,
    00133   .vbp= 10,
    00134   .vfp= 10,
    00135   .vhdly= 0,
    00136 };
    00137
    00138
    00142 void lcd_pio_config(void)
    00143 {
    00144   static const gpio_map_t piomap= {
    00145     { AVR32_LCDC_CC_0_0_PIN, AVR32_LCDC_CC_0_0_FUNCTION },
    00146     { AVR32_LCDC_DVAL_0_0_PIN, AVR32_LCDC_DVAL_0_0_FUNCTION },
    00147     { AVR32_LCDC_HSYNC_0_PIN, AVR32_LCDC_HSYNC_0_FUNCTION },
    00148     { AVR32_LCDC_MODE_0_0_PIN, AVR32_LCDC_MODE_0_0_FUNCTION },
    00149     { AVR32_LCDC_PCLK_0_PIN, AVR32_LCDC_PCLK_0_FUNCTION },
    00150     { AVR32_LCDC_PWR_0_PIN, AVR32_LCDC_PWR_0_FUNCTION },
    00151     { AVR32_LCDC_VSYNC_0_PIN, AVR32_LCDC_VSYNC_0_FUNCTION },
    00152     { AVR32_LCDC_DATA_0_0_PIN, AVR32_LCDC_DATA_0_0_FUNCTION },
    00153     { AVR32_LCDC_DATA_1_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
    00154     { AVR32_LCDC_DATA_2_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
    00155     { AVR32_LCDC_DATA_3_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
    00156     { AVR32_LCDC_DATA_4_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
    00157     { AVR32_LCDC_DATA_5_PIN, AVR32_LCDC_DATA_5_FUNCTION },
    00158     { AVR32_LCDC_DATA_6_PIN, AVR32_LCDC_DATA_6_FUNCTION },
    00159     { AVR32_LCDC_DATA_7_PIN, AVR32_LCDC_DATA_7_FUNCTION },
    00160     { AVR32_LCDC_DATA_8_0_PIN, AVR32_LCDC_DATA_8_0_FUNCTION },
    00161     { AVR32_LCDC_DATA_9_0_PIN, AVR32_LCDC_DATA_9_0_FUNCTION },
    00162     { AVR32_LCDC_DATA_10_0_PIN, AVR32_LCDC_DATA_10_0_FUNCTION },
    00163     { AVR32_LCDC_DATA_11_0_PIN, AVR32_LCDC_DATA_11_0_FUNCTION },
    00164     { AVR32_LCDC_DATA_12_0_PIN, AVR32_LCDC_DATA_12_0_FUNCTION },
    00165     { AVR32_LCDC_DATA_13_PIN, AVR32_LCDC_DATA_13_FUNCTION },
    00166     { AVR32_LCDC_DATA_14_PIN, AVR32_LCDC_DATA_14_FUNCTION },
    00167     { AVR32_LCDC_DATA_15_PIN, AVR32_LCDC_DATA_15_FUNCTION },
    00168     { AVR32_LCDC_DATA_16_0_PIN, AVR32_LCDC_DATA_16_0_FUNCTION },
    00169     { AVR32_LCDC_DATA_17_0_PIN, AVR32_LCDC_DATA_17_0_FUNCTION },
    00170     { AVR32_LCDC_DATA_18_0_PIN, AVR32_LCDC_DATA_18_0_FUNCTION },
    00171     { AVR32_LCDC_DATA_19_0_PIN, AVR32_LCDC_DATA_19_0_FUNCTION },
    00172     { AVR32_LCDC_DATA_20_0_PIN, AVR32_LCDC_DATA_20_0_FUNCTION },
    00173     { AVR32_LCDC_DATA_21_0_PIN, AVR32_LCDC_DATA_21_0_FUNCTION },
    00174     { AVR32_LCDC_DATA_22_PIN, AVR32_LCDC_DATA_22_FUNCTION },
    00175     { AVR32_LCDC_DATA_23_PIN, AVR32_LCDC_DATA_23_FUNCTION }
    00176   };
    00177   gpio_enable_module(piomap, 31);
    00178 }
    00179
    00180
    00185 void fill_frame_buffer (lcdc_conf_t *lcdc_conf)
    00186 {
    00187   U32 k,l,x,y;
    00188   volatile U8 * framePtr = (U8 *) (lcdc_conf->dmabaddr1 | 0xA0000000);
    00189
    00190   for (l=0; l < lcdc_conf->yres; l++){        // line
    00191     for (k=0; k < lcdc_conf->xres; k++)    // column
    00192     {
    00193       x = (255 * l) / lcdc_conf->yres;
    00194       y = (255 * k) / lcdc_conf->xres;
    00195       *framePtr++ = x;
    00196       *framePtr++ = y;
    00197       *framePtr++ = 255 - (x + y) / 2;
    00198     }
    00199   }
    00200 }
    00201
    00202
    00208 void init_spiMaster(volatile avr32_spi_t * spi, long cpuHz)
    00209 {
    00210   gpio_map_t spi_piomap = {          \
    00211     {AVR32_SPI0_SCK_0_PIN, AVR32_SPI0_SCK_0_FUNCTION},  \
    00212     {AVR32_SPI0_MISO_0_PIN, AVR32_SPI0_MISO_0_FUNCTION},  \
    00213     {AVR32_SPI0_MOSI_0_PIN, AVR32_SPI0_MOSI_0_FUNCTION},  \
    00214     {AVR32_SPI0_NPCS_0_PIN, AVR32_SPI0_NPCS_0_FUNCTION},  \
    00215     {AVR32_SPI0_NPCS_1_PIN, AVR32_SPI0_NPCS_1_FUNCTION},  \
    00216     {AVR32_SPI0_NPCS_2_PIN, AVR32_SPI0_NPCS_2_FUNCTION},  \
    00217     {AVR32_SPI0_NPCS_3_PIN, AVR32_SPI0_NPCS_3_FUNCTION},  \
    00218   };
    00219   gpio_enable_module(spi_piomap, 7);
    00220
    00221   spi_options_t spiOptions = {
    00222     .reg = 1,
    00223     .baudrate = 1500000,
    00224     .bits = 8,
    00225     .spck_delay = 0,
    00226     .trans_delay = 0,
    00227     .stay_act = 1,
    00228     .spi_mode = 3,
    00229     .modfdis = 0,
    00230   };
    00231
    00232   /* Initialize as master */
    00233   spi_initMaster(spi, &spiOptions);
    00234
    00235   /* Set master mode; variable_ps, pcs_decode, delay */
    00236   spi_selectionMode(spi, 0, 0, 0);
    00237
    00238   /* Select slave chip 1 (SPI_NPCS1) */
    00239   spi_selectChip(spi, 1);
    00240
    00241   spi_setupChipReg(spi, &spiOptions, cpuHz);
    00242
    00243   spi_enable(spi);
    00244 }
    00245
    00246
    00250 int main (void)
    00251 {
    00252   volatile avr32_spi_t *spi = &AVR32_SPI0;
    00253
    00254   // Reset PM. Makes sure we get the expected clocking after a soft reset (e.g.: JTAG reset)
    00255   pm_reset();
    00256
    00257   // Start PLL0 giving 80 MHz clock
    00258   pm_pll_opt_t pll_opt = {
    00259     .pll_id = 0,
    00260     .mul = 4,
    00261     .div = 1,
    00262     .osc_id = 0,
    00263     .count = 16,
    00264     .wait_for_lock = 1,
    00265   };
    00266   pm_start_pll(&pll_opt);
    00267
    00268   // Divide HSB by 2, PBB by 2 and PBA by 4 to keep them below maximum ratings
    00269   pm_set_clock_domain_scaler(PM_HSB_DOMAIN, 2);
    00270   pm_set_clock_domain_scaler(PM_PBB_DOMAIN, 2);
    00271   pm_set_clock_domain_scaler(PM_PBA_DOMAIN, 4);
    00272
    00273   pm_set_mclk_source(PM_PLL0);
    00274
    00275   init_dbg_rs232(pm_read_module_freq_hz(PM_PBA_USART1));
    00276   print_dbg("\nCPU running at ");
    00277   print_dbg_ulong(pm_get_mclk_freq_hz()/1000000);
    00278   print_dbg(" MHz\n");
    00279   sdramc_init(pm_read_module_freq_hz(PM_PBB_HSDRAMC));
    00280   print_dbg("Board init complete\n");
    00281
    00282   print_dbg("Setting up SPI for LTV350QV panel\n");
    00283   init_spiMaster(spi, pm_read_module_freq_hz(PM_PBA_SPI0));
    00284   print_dbg("Initializing LTV350QV panel\n");
    00285   ltv350qv_power_on(spi, 1);
    00286   print_dbg("Setting up LCD controller\n");
    00287   lcd_pio_config();
    00288
    00289   // Enable CLOCK for LCDC in HSBMASK
    00290   pm_enable_module(PM_HSB_LCDC);
    00291
    00292   // Enable generic clock PLL0 for LCD controller pixel clock
    00293   pm_gen_clk_opt_t gen_clk_opt = {
    00294     .clock_source = PM_PLL0,
    00295     .divider = 2,
    00296   };
    00297   pm_start_generic_clock(7, &gen_clk_opt);
    00298
    00299   lcdc_init(&ltv350qv_conf);
    00300
    00301   print_dbg("Testing frame buffer\n");
    00302
    00303   // clear framebuffer
    00304   memset((void *)ltv350qv_conf.dmabaddr1, 0, ltv350qv_conf.xres * ltv350qv_conf.yres * ltv350qv_conf.pixelsize / 8);
    00305
    00306   fill_frame_buffer(&ltv350qv_conf);
    00307
    00308   while(1);
    00309 }