# sdramc_example.c File Reference

## Detailed Description

SDRAMC on EBI example application.

- Compiler: IAR EWAVR32 and GNU GCC for AVR32
- Supported devices: All AVR32 devices with an SDRAMC module can be used.
- AppNote:

Author:
  Atmel Corporation: http://www.atmel.com
  Support and FAQ: http://support.atmel.no/

Definition in file sdramc_example.c.

`#include "print_funcs.h"`
`#include "pm_at32ap7000.h"`
`#include "board.h"`
`#include "gpio.h"`
`#include "sdramc_at32ap7000.h"`

Go to the source code of this file.

## Functions
int | main (void)

## Function Documentation

int main | ( | void |  | ) |

This function will setup the the SDRAM controller, intialize the SDRAM found on the STK1000 and test it.

Returns:
  The number of errors

Definition at line 101 of file sdramc_example.c.

References sdramc_init().

    00102 {
    00103   U32 i, sdram_size, tmp;
    00104   U32 noErrors=0;
    00105   volatile U32 *sdram = (void *) BOARD_SDRAM_BASE;
    00106
    00107 #if BOARD == STK1000
    00108   // Reset PM. Makes sure we get the expected clocking after a soft reset (e.g.: JTAG reset)
    00109   pm_reset();
    00110
    00111   // Start PLL0 giving 80 MHz clock
    00112   pm_pll_opt_t pll_opt ={
    00113     .pll_id = 0,
    00114     .mul = 4,
    00115     .div = 1,
    00116     .osc_id = 0,
    00117     .count = 16,
    00118     .wait_for_lock = 1,
    00119   };
    00120   pm_start_pll(&pll_opt);
    00121
    00122   // Divide HSB by 2, PBB by 2 and PBA by 4 to keep them below maximum ratings
    00123   pm_set_clock_domain_scaler(PM_HSB_DOMAIN, 2);
    00124   pm_set_clock_domain_scaler(PM_PBB_DOMAIN, 2);
    00125   pm_set_clock_domain_scaler(PM_PBA_DOMAIN, 4);
    00126
    00127   pm_set_mclk_source(PM_PLL0);
    00128 #endif
    00129
    00130   init_dbg_rs232(pm_read_module_freq_hz(PM_PBA_USART1));
    00131   print_dbg("Board running at ");
    00132   print_dbg_ulong(pm_get_mclk_freq_hz()/1000000);
    00133   print_dbg(" MHz\n");
    00134   print_dbg("Initializing SDRAM...");
    00135   sdramc_init(pm_read_module_freq_hz(PM_PBB_HSDRAMC));
    00136   print_dbg("done\n\n");
    00137
    00138   /* setup sdram_size */
    00139   sdram_size = 1 << (SDRAM_COL_BITS + SDRAM_ROW_BITS + SDRAM_BANK_BITS + 2);
    00140
    00141 /* test the chip */
    00142   for (i = 0; i < sdram_size; i++){
    00143
    00144     sdram[i] = i;
    00145     tmp = sdram[i];
    00146
    00147     if(i != tmp) {
    00148       noErrors++;
    00149       print_dbg("ERROR at 0x");
    00150       print_dbg_hex((U32) &sdram[i]);
    00151       print_dbg("\n");
    00152       }
    00153     }
    00154   if (noErrors == 0)
    00155     print_dbg("SDRAM test successfully completed\n");
    00156   else{
    00157     print_dbg("SDRAM test completed with ");
    00158     print_dbg_ulong(noErrors);
    00159     print_dbg(" errors out of ");
    00160     print_dbg_ulong(i);
    00161     print_dbg(" tests\n");
    00162   }
    00163
    00164   while(1);
    00165 }