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\begin_layout Plain Layout
0.18
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2.5
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9-12-2023
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Move to new release of CTU CAN FD.
 Bump document version accordingly.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0.19
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2.6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
29-03-2025
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Replace GHDL with NVC
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0.20
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2.6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
15-6-2025
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Clean-up.
 Add missing RX buffer FSM states.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Standard
\begin_inset CommandInset toc
LatexCommand tableofcontents

\end_inset


\end_layout

\begin_layout Standard
\begin_inset ERT
status open

\begin_layout Plain Layout

% classis page numbering
\end_layout

\begin_layout Plain Layout


\backslash
mainmatter
\end_layout

\end_inset


\end_layout

\begin_layout Chapter*
Format
\end_layout

\begin_layout Standard
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
addcontentsline{toc}{chapter}{Format}
\end_layout

\end_inset


\end_layout

\begin_layout Standard
Throughout this document following notations are kept:
\end_layout

\begin_layout Itemize
Common text is written with this font.
\end_layout

\begin_layout Itemize
Memory registers are always described with capital letters e.g.
 REGISTER or REGISTER [BIT_FIELD] to represent register or bit field within
 a register.
\end_layout

\begin_layout Itemize
Signal names and generic names are written by bold lower-case cursive (e.g.
 
\series bold
\shape italic
can_rx
\series default
\shape default
)
\end_layout

\begin_layout Itemize
Explicit terms from ISO11898-1 2015 are marked via red color (e.g.
 
\color red
SOF
\color inherit
 bit).
 Definition of these terms can be found in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Itemize
Open issues and TODOs are written in blue font like so 
\color blue
TODO: not yet implemented.
\end_layout

\begin_layout Chapter
General Information
\end_layout

\begin_layout Standard
\begin_inset ERT
status open

\begin_layout Plain Layout

 
\backslash
thispagestyle{fancy}
\end_layout

\end_inset


\end_layout

\begin_layout Section
Introduction
\end_layout

\begin_layout Standard
This document describes architecture of CTU CAN FD IP Core.
 It describes external interfaces of the core as well as internal architecture.
 This document does not provide functional description of the core, reffer
 to CTU CAN FD Datasheet (
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

) for such information.
 This document alogn with CTU CAN FD Datasheet (
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

) serves as reference on how shall CTU CAN FD function, and it is supposed
 to be used as verification reference on how shall the device behave.
\end_layout

\begin_layout Section
Development tools
\end_layout

\begin_layout Standard
To develop CTU CAN FD following tools are used:
\end_layout

\begin_layout Itemize
NVC for digital simulations.
\end_layout

\begin_layout Itemize
Quartus Prime and Xilinx Vivado for Synthesis to Intel and Xilinx FPGAs,
 Timing analysis and design size benchmarks.
\end_layout

\begin_layout Itemize
VUnit for simulation wrappers.
\end_layout

\begin_layout Itemize
Kactus2 for definition of register map in IP-XACT format.
\end_layout

\begin_layout Itemize
\SpecialChar LyX
 to write documentation.
\end_layout

\begin_layout Itemize
GitLab of CTU FEE and Github to host source code GIT repository.
\end_layout

\begin_layout Itemize
Wavedrom for Timing Diagrams.
\end_layout

\begin_layout Itemize
Python for scripting.
\end_layout

\begin_layout Section
Design automation
\end_layout

\begin_layout Standard
Part of CTU CAN FD Core is auto-generated.
 Register map is implemented in Kactus 2 in IP-XACT format (
\begin_inset Quotes eld
\end_inset

spec/ CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml
\begin_inset Quotes erd
\end_inset

).
 The design in IP-XACT format is unified specification of user-interface.
 Following resources are generated from IP-XACT specification:
\end_layout

\begin_layout Itemize
VHDL packages with address, bit-fields and reset values definitions 
\begin_inset Newline newline
\end_inset

(
\begin_inset Quotes eld
\end_inset

src/lib/can_fd_frame_format.vhd
\begin_inset Quotes erd
\end_inset

, 
\begin_inset Quotes eld
\end_inset

src/lib/can_fd_register_map.vhd
\begin_inset Quotes erd
\end_inset

).
\end_layout

\begin_layout Itemize
C header file with address map definitions and register descriptions 
\begin_inset Newline newline
\end_inset

(
\begin_inset Quotes eld
\end_inset

driver/ctu_can_fd_regs.h
\begin_inset Quotes erd
\end_inset

, 
\begin_inset Quotes eld
\end_inset

driver/ctu_can_fd_frame.h
\begin_inset Quotes erd
\end_inset

).
\end_layout

\begin_layout Itemize
Lyx documentation of register map.
 Reffer to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

.
\end_layout

\begin_layout Itemize
RTL Code of Control Registers module (
\begin_inset Quotes eld
\end_inset

src/memory_registers/generated/*).
\end_layout

\begin_layout Itemize
Documentation of RTL module interfaces (
\begin_inset Quotes eld
\end_inset

doc/core/entity_docs
\begin_inset Quotes erd
\end_inset

).
\end_layout

\begin_layout Standard
To generate these design materials CTU CAN FD IP Core uses IP-XACT register
 map generator which is accessible at 
\begin_inset CommandInset href
LatexCommand href
name "regmap_gen"
target "https://github.com/Blebowski/Reg_Map_Gen"
literal "false"

\end_inset

.
 Register map generator is linked as sub-module of CTU CAN FD repository.
 Clone all the submodules recursively before using register map generator.
 All of the generated files are considered as don't touch.
 Part of this document is also auto-generated.
 Each section which describes list of Generics and Signals of a module is
 generated from VHDL RTL code.
\end_layout

\begin_layout Subsection
Register map generation
\end_layout

\begin_layout Standard
When CTU CAN FD GIT repository is clonned, register map can be generated
 by following script:
\end_layout

\begin_layout Verbatim
cd scripts
\end_layout

\begin_layout Verbatim
./update_reg_map
\end_layout

\begin_layout Subsection
Xilinx Vivado component
\end_layout

\begin_layout Standard
CTU CAN FD contains Xilinx Vivado component (
\begin_inset Quotes eld
\end_inset

src/component.xml
\begin_inset Quotes erd
\end_inset

) for integration of CTU CAN FD to Xilinx based FPGAs.
 Xilinx Vivado component is generated by following script:
\end_layout

\begin_layout Verbatim
cd scripts
\end_layout

\begin_layout Verbatim
python gen_vivado_component.py
\end_layout

\begin_layout Section
General coding guidlines
\end_layout

\begin_layout Standard
RTL code within CTU CAN FD has following coding rules:
\end_layout

\begin_layout Itemize
Underscore is always used to separate words within signal/entity/process/variabl
e/port/generic names (e.g.
 tx_hw_cmd, can_core).
\end_layout

\begin_layout Itemize
Constants are written by capital letters with 
\begin_inset Quotes eld
\end_inset

C_
\begin_inset Quotes erd
\end_inset

 prefix (e.g.
 C_SUSPEND_DURATION).
\end_layout

\begin_layout Itemize
Generics are written by capital letters with 
\begin_inset Quotes eld
\end_inset

G_
\begin_inset Quotes erd
\end_inset

 prefix (e.g.
 G_RX_BUFF_SIZE).
 This rule has an exception on top level interface and wrappers of CTU CAN
 FD (can_top_level, can_top_ahb).
\end_layout

\begin_layout Itemize
Signals are always commented on line before the signal.
 This must be especially true for port signals.
 This allows to extract documentation of VHDL entities from RTL code.
\end_layout

\begin_layout Itemize
Sections of signals can be defined by surrounding section name by whole
 line of 
\begin_inset Quotes eld
\end_inset

-
\begin_inset Quotes erd
\end_inset

 characters.
\end_layout

\begin_layout Itemize
All RTL codes are indented with 4 spaces.
\end_layout

\begin_layout Itemize
Line length shall be limited to 80 characters.
\end_layout

\begin_layout Itemize
Instance names are suffixed with 
\begin_inset Quotes eld
\end_inset

_inst
\begin_inset Quotes erd
\end_inset

, process names are suffixed with 
\begin_inset Quotes eld
\end_inset

_proc
\begin_inset Quotes erd
\end_inset

, cover point names are suffixed with 
\begin_inset Quotes eld
\end_inset

_cov
\begin_inset Quotes erd
\end_inset

, assertion names are suffixed with 
\begin_inset Quotes eld
\end_inset

_asrt
\begin_inset Quotes erd
\end_inset

.
 DFF names can be suffixed by 
\begin_inset Quotes eld
\end_inset

_d/_q
\begin_inset Quotes erd
\end_inset

 depending on whether it is DFF input/output.
\end_layout

\begin_layout Section
Source code access
\end_layout

\begin_layout Standard
CTU CAN FD IP Core source code is available in CTU FEE GitLab repository
 at:
\end_layout

\begin_layout Standard
\begin_inset space \qquad{}
\end_inset


\begin_inset CommandInset href
LatexCommand href
name "https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core"
target "https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core"
literal "false"

\end_inset


\end_layout

\begin_layout Section
ISO11898-1 2015 compliance
\end_layout

\begin_layout Standard
CTU CAN FD is compliant with 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
 With regards to this document, CTU CAN FD supports all implementation options
 (Classical CAN, CAN FD Tolerant, CAN FD enabled).
 Compliance to each of these options can be configured via a register (run-time
 configurable).
 Reffer to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

 for description of CTU CAN FD configuration.
\end_layout

\begin_layout Standard
Support of optional features from 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

 is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:iso-optional-features"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:iso-optional-features-1"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="14" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="15.5line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="65line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Feature Name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Status
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Notes
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FD Frame format
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Disabling of frame formats
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reception of CAN FD frames can be disabled by setting MODE[FDE] = '0'.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Limited LLC frames
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Not Supported
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Only full size (64 byte) frames are supported.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No transmission of frames including padding bytes
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Not Supported
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No padding is inserted since full sized frames are supported.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
LLC Abort Interface
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Issuing Set abort command to TXT buffer which is used for transmission is
 equal to issuing 
\color red
LData.Abort_Request
\color inherit
 /
\color red
 LRemote.Abort_Request
\color inherit
 primitive.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ESI and BRS values
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BRS value can be specified for each transmitted CAN frame.
 ESI value can't be specified for transmitted CAN frames, it is always derived
 from current Fault confinement state of CTU CAN FD.
 ESI value can be read for each received frame.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Method to provide MAC data consistency
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Partially Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTU CAN FD implements TXT buffer RAMs which stores whole CAN frame for transmiss
ion before the transmission is started.
 This corresponds to: 
\begin_inset Quotes eld
\end_inset

The MAC sub-layer shall store the whole message to be transmitted in a temporary
 buffer that is filled before the transmission is started.
\begin_inset Quotes erd
\end_inset

 Additionally, CTU CAN FD implements parity protection on each word of TXT
 buffer and RX buffer if 
\series bold
\shape italic
sup_parity
\series default
\shape default
=true.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Time and time triggering
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Partially Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Time triggerred transmission is available in TX Arbitrator module.
 CTU CAN FD does not support time base by itself, it is left up to integrator
 to provide Time base via 
\series bold
\shape italic
timestamp
\series default
\shape default
 input.
 The reason for this, is to share single Time base between multiple instances
 of CTU CAN FD.
 
\series bold
\shape italic
timestamp
\series default
\shape default
 input is readable from CTU CAN FD.
 No event generation is provided from 
\series bold
\shape italic
timestamp
\series default
\shape default
 input.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Time stamping
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamping of RX frames is supported in SOF or EOF bit.
 Time Base counter must be provided by integrator and must be connected
 to 
\series bold
\shape italic
timestamp
\series default
\shape default
 input.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus Monitoring mode
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported via MODE[LOM].
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Handle
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Handle corresponds to TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Restricted operation
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported via MODE[ROM].
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Separate prescalers for Nominal and Data Bit Rate
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Prescalers are separate in BTR[BRP] and BTR_FD[BRP_FD] registers.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
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ISO11989-1 optional features (1)
\begin_inset CommandInset label
LatexCommand label
name "tab:iso-optional-features"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

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cellcolor{gray}
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\end_layout

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Supported via SETTINGS[RTRLE] and SETTINGS[RTRTH] registers.
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Disabling of protocol exception event on res bit detected recessive
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Protocol exception is configurable via SETTINGS[PEX] register.
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CTU CAN FD supports both 
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
 bit rate.
\end_layout

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Edge filtering during the bus integration state
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\begin_inset Text

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\color red
Secondary sample point
\color inherit
 position is always given in 
\color red
minimum time quanta
\color inherit
 regardless of bit rate prescaler seettings.
\end_layout

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\end_layout

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\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
ISO11989-1 optional features (1)
\begin_inset CommandInset label
LatexCommand label
name "tab:iso-optional-features-1"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Chapter
Interfaces
\end_layout

\begin_layout Standard
\begin_inset ERT
status open

\begin_layout Plain Layout

 
\backslash
thispagestyle{fancy}
\end_layout

\end_inset


\end_layout

\begin_layout Section
Memory Bus
\end_layout

\begin_layout Standard
CTU CAN FD is a slave device accessible via one of three memory buses:
\end_layout

\begin_layout Itemize
RAM-like interface
\end_layout

\begin_layout Itemize
APB
\end_layout

\begin_layout Itemize
AHB
\end_layout

\begin_layout Standard
Each interface can be used via dedicated wrapper.
 SW shall not access CTU CAN FD sooner than two clock cycles after external
 reset was released (due to reset synchronisation) (see Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:reset-description"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 If CTU CAN FD is accessed earlier, writes accesses have no effect and read
 accesses return zeroes.
 If external reset is executed via SW driver (e.g.
 at driver load time), it is recomended to add corresponding delay before
 driver executes any access to the device (e.g.
 via usleep, nanosleep, dummy NOPs, or similar mechanism).
\end_layout

\begin_layout Subsection
RAM-like interface
\begin_inset CommandInset label
LatexCommand label
name "subsec:RAM-like-interface"

\end_inset


\end_layout

\begin_layout Description
Wrapper can_top_level.vhd
\end_layout

\begin_layout Standard
RAM-like interface is the default interface of CTU CAN FD with signals shown
 in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:RAM-like-interface"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 A typical read/write transcations on RAM-like interface are shown in Figure
 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:ram-like-interface"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Note that RAM-like interface does not contain any Ready/ACK signal.
 CTU CAN FD is always able to process written data in one clock cycle (write
 access) and return read data in the next clock cycle (read access).
 Accesses on RAM-like interface shall be 4 byte aligned (lower 2 bits of
 address shall be equal to 0).
 If access is not 4 byte aligned, lower 2 bits of address are ignored.
 Therefore, single access spaning more than 1 32 bit memory word is not
 possible.
 Each byte is separately writable and readable via byte enable (
\series bold
\shape italic
sbe
\series default
\shape default
), therefore 8-bit and 16-bit accesses are supported.
 If 
\series bold
\shape italic
sbe
\series default
\shape default
 signal is zero, data on corresponding byte are not written during write
 access, and zeroes are returned during read access.
 CTU CAN FD is little endian oriented (LSB = Lowest Adress -> 
\series bold
\shape italic
sbe(0)
\series default
\shape default
 = Byte 0 = 
\series bold
\shape italic
data_in/out (7:0)
\series default
\shape default
; 
\series bold
\shape italic
sbe (3)
\series default
\shape default
 = Byte 3 = 
\series bold
\shape italic
data_in/out(31:24)
\series default
\shape default
).
\end_layout

\begin_layout Standard
RAM-like interface supports burst read from RX buffer (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:RX-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 In such case, 
\series bold
\shape italic
address
\series default
\shape default
 input must be equal to RX_DATA register address during whole read operation
 (
\begin_inset Quotes eld
\end_inset

stationary
\begin_inset Quotes erd
\end_inset

/
\begin_inset Quotes erd
\end_inset

frozen
\begin_inset Quotes erd
\end_inset

 burst).
 During such read, each word must be read by 32-bit access (
\series bold
\shape italic
sbe
\series default
\shape default
=
\begin_inset Quotes erd
\end_inset

1111
\begin_inset Quotes erd
\end_inset

).
 This means that read from RX buffer is always executed by 32-bit word regardles
s of 
\series bold
\shape italic
sbe
\series default
\shape default
 value.
 Such a situation is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-buffer-burst-read"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
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\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
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<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="10text%">
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Signal Name
\begin_inset ERT
status open

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\backslash
cellcolor{gray}
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\end_layout

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Direction
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status open

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\end_layout

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Chip Select
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4
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Byte enable (applicable for both reads and writes)
\end_layout

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\series bold
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out
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Read data
\end_layout

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</cell>
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\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RAM-like interface
\begin_inset CommandInset label
LatexCommand label
name "tab:RAM-like-interface"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/ram_like.pdf
	lyxscale 20
	scale 75

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RAM-like interface
\begin_inset CommandInset label
LatexCommand label
name "fig:ram-like-interface"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
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	filename ../pics/Timing_diagrams/PDFs/ram_like_fifo_read.pdf
	lyxscale 20
	scale 66

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\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer burst read
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-burst-read"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
RAM-like interface is Avalon compatible (according to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-3"
literal "false"

\end_inset

) and mapping of RAM like signals to Avalon Memory-mapped slave signals
 is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:RAM-like-avalon-mappping"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When connected to Avalon MM master, write access to reserved address has
 no effect and read access returns all zeroes instead of responding with
 DECODEERROR response.
 
\series bold
\shape italic
response
\series default
\shape default
 signal shall be connected to 
\begin_inset Quotes eld
\end_inset

00
\begin_inset Quotes erd
\end_inset

, 
\series bold
\shape italic
writeresponsevalid
\series default
\shape default
 and 
\series bold
\shape italic
readdatavalid
\series default
\shape default
 shall be connected to '1'.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="8" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15text%">
<column alignment="left" valignment="top" width="15text%">
<column alignment="left" valignment="top" width="61.5text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RAM-like signal name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
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Avalon signal name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

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\end_layout

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</cell>
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\begin_inset Text

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Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

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\end_layout

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</cell>
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\begin_inset Text

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\series bold
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\end_layout

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</cell>
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\begin_inset Text

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\series bold
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\begin_inset Text

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Data written to Avalon MM slave.
\end_layout

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\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Address for read/write of Avalon MM slave.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
scs
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Shall correspond to chip select of slave if more than 1 slave is connected
 to given bus.
 If single slave is connected, shall be connected to 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
srd
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
read
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read indication
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
swr
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
write
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write indication
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sbe
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
byteenable
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Byte enable, used for both read and write transfers.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
data_out
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
readdata
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data read from Avalon MM slave.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RAM-like to Avalon mapping
\begin_inset CommandInset label
LatexCommand label
name "tab:RAM-like-avalon-mappping"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
APB
\end_layout

\begin_layout Description
Wrapper can_top_apb.vhd
\end_layout

\begin_layout Standard
APB Wrapper is compatible with 
\begin_inset CommandInset citation
LatexCommand cite
key "key-4"
literal "false"

\end_inset

.
 Signals of CTU CAN FD on APB interface are shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:apb-interface"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Every access on APB Interface lasts two clock cycles, APB does not support
 bursts.
 CTU CAN FD never stalls on APB interface via 
\series bold
\shape italic
s_apb_pready
\series default
\shape default
, it keeps 
\series bold
\shape italic
s_apb_pready
\series default
\shape default
 always high.
 CTU CAN FD does not return error via 
\series bold
\shape italic
s_apb_pslverr
\series default
\shape default
 on any access.
 If SW executes access to an invalid location within CTU CAN FD, it is simply
 ignored.
 This allows dumping whole CTU CAN FD memory space without memory access
 errors.
 Accesses on APB Interface shall be 4 byte aligned.
 If access is not 4 byte aligned, lowest 2 bits of address are ignored.
 8/16 bit write accesses are supported via write strobe signal (
\series bold
\shape italic
s_apb_pstrb
\series default
\shape default
).
 Basic accesses on APB are shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:apb-interface-access"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="11" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="17text%">
<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="52text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal Name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Direction
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Width
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_paddr
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Address
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_penable
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Enable.
 Indicates second cycle of access.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_prot
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protection type.
 Ignored by CTU CAN FD.
 All access types are treated equally by CTU CAN FD.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_prdata
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read data.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_pready
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Ready.
 Always asserted.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_psel
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Slave select.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_pslverr
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Access error.
 CTU CAN FD always drives this pin low.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_pstrb
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write Strobe.
 During write access, logic 1 indicates according byte will be written.
 Ignored during read access.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_pwdata
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write data.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
s_apb_pwrite
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Access direction.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
APB interface
\begin_inset CommandInset label
LatexCommand label
name "tab:apb-interface"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/apb_access.pdf
	lyxscale 20
	scale 75

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
APB Interface access
\begin_inset CommandInset label
LatexCommand label
name "fig:apb-interface-access"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
AHB
\end_layout

\begin_layout Description
Wrapper CAN_top_ahb.vhd
\end_layout

\begin_layout Standard
AHB Wrapper is compatible with 
\begin_inset CommandInset citation
LatexCommand cite
key "key-5"
literal "false"

\end_inset

.
 Signals of CTU CAN FD on AHB interface are shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ahb-interface"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 CTU CAN FD accepts all transfer types (Non-sequential, Sequential, Idle,
 Busy) on AHB bus.
 CTU CAN FD treats burst accesses equally as regular accesses (no internal
 caching is done).
 If read transfer occurs after write transfer (directly one after another),
 CTU CAN FD inserts one wait cycle into AHB transaction, as is shown in
 Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:ahb-interface-access"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 CTU CAN FD does not return error via 
\series bold
\shape italic
hresp
\series default
\shape default
 on any accesses.
 If SW executes access to an invalid location within CTU CAN FD, it is simply
 ignored.
 This allows dumping whole CTU CAN FD memory space without memory access
 errors.
 CTU CAN FD does not support unaligned accesses on AHB Bus.
 Each access shall be aligned to its own size (8-bit access can have arbitrary
 address, 16 bit access must have address 2-byte aligned, 32-bit access
 must have address 4-byte aligned).
 No locked sequences (
\series bold
\shape italic
hmastlock
\series default
\shape default
) are supported by CTU CAN FD.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="14" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="17text%">
<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="52text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal Name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Direction
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Width
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
haddr
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Address
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hwdata
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write Data
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hsel
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write select
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hwrite
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Access direction
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hsize
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Access size.
 (8/16/32 bit access sizes are supported).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hburst
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Burst indication, ignored by CTU CAN FD.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hprot
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protection type, ignored by CTU CAN FD.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
htrans
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transaction type.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hmastlock
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Locked sequence indication.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hready
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Ready indication.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hreadyout
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Ready indication output.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hresp
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Response type.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hrdata
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read data.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
AHB interface
\begin_inset CommandInset label
LatexCommand label
name "tab:ahb-interface"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/ahb_access.pdf
	lyxscale 20
	scale 75

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
AHB Interface access
\begin_inset CommandInset label
LatexCommand label
name "fig:ahb-interface-access"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Limitations on 8/16 bit buses
\end_layout

\begin_layout Standard
CTU CAN FD is 32-bit peripheral, however, it is possible to integrate it
 to systems with 8/16 bit bus thanks to 
\begin_inset Quotes eld
\end_inset

byte enable
\begin_inset Quotes erd
\end_inset

 capabilities of each bus interface wrapper.
 If SW accesses CTU CAN FD via 8/16 bit bus, access to simple 32-bit R/W
 register can be split into 4/2 consecutive accesses without affecting the
 functionality.
 However, due to side-effects on several registers, there are following
 limitations when accessing CTU CAN FD from 8/16 bit buses:
\end_layout

\begin_layout Itemize
CTU CAN FD must be used in RX buffer manual mode (MODE[RXBAM] = 0).
 This is necessary since read of single word from RX buffer can not be done
 by single read access to RX_DATA register.
 On 8 bit systems, it will require 4 reads (addresses RX_DATA ..
 RX_DATA + 0x3), on 16 bit systems it will require 2 reads (addresses RX_DATA
 and RX_DATA + 0x2).
 Since each read from RX_DATA register in RX buffer automated mode (MODE[RXBAM]
 = 1), will move RX buffer read pointer, the rest of the memory word would
 be lost without being read out.
 Thus it would be impossible to correctly read out received frames.
 Reading out RX buffer on 8/16 bit systems thus requires operation in MODE[RXBAM
] = 0 and manually moving RX buffer read pointer by COMMAND[RXRPMV] bit.
\end_layout

\begin_layout Itemize
On 8 bit systems, TX_PRIORITY register is only able to change priority of
 TXT buffers atomically if number of TXT buffers is 2.
 On 16 bit systems, TX_PRIORITY register is only able to change priority
 of TXT buffers atomically, if number of TXT buffers is 2-4.
 Atomic change of TXT buffer priorities is required if TXT buffers are used
 like a FIFOs by priority rotation (such approach is used by CTU CAN FD
 Linux driver).
 Thus, if TXT buffer priorities need to be rotated atomically, following
 restrictions apply:
\end_layout

\begin_deeper
\begin_layout Itemize
On 8 bit systems, only 2 TXT buffers must be used.
\end_layout

\begin_layout Itemize
On 16 bit systems, only up to 4 TXT buffers must be used.
\end_layout

\begin_layout Itemize
If atomic rotation of priorities is not required, number of TXT buffers
 is not restricted.
\end_layout

\end_deeper
\begin_layout Section
CAN Bus
\end_layout

\begin_layout Standard
CTU CAN FD interfaces to physical layer transceiver via 
\series bold
\shape italic
can_rx
\series default
\shape default
 and 
\series bold
\shape italic
can_tx
\series default
\shape default
 pins.
 
\series bold
\shape italic
can_rx
\series default
\shape default
 input is assumed to be asynchronous to System clock (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Clock-and-reset"
plural "false"
caps "false"
noprefix "false"

\end_inset

) and it is treated like asynchronous signal.
 
\series bold
\shape italic
can_tx
\series default
\shape default
 output is synchronous to System clock.
 
\series bold
\shape italic
can_tx
\series default
\shape default
 output is glitch-free during operation on CAN bus as long as MODE[LOM]
 bit is not changed.
\end_layout

\begin_layout Section
Timestamp
\end_layout

\begin_layout Standard
CTU CAN FD interfaces to system level Time base via 
\series bold
\shape italic
timestamp
\series default
\shape default
 input.
 
\series bold
\shape italic
timestamp
\series default
\shape default
 input is assumed to be synchronous to System clock, and therefore there
 is no resynchronization on this input.
 If 
\series bold
\shape italic
timestamp
\series default
\shape default
 is unused (no Timestamping / Time Triggering capability), it shall be driven
 to 0xFFFF FFFF FFFF FFFF.
 If 
\series bold
\shape italic
timestamp
\series default
\shape default
 is used, it shall be driven by unsigned up-counting counter which measures
 flow of time within a system to which CTU CAN FD is being integrated.
 
\series bold
\shape italic
timestamp
\series default
\shape default
 does not need to be incremented every clock cycle of System clock, nor
 there is a constraint on step that it is incremented with, it only needs
 to be synchronous to System clock.
 If system level time counter has lower width than 64 bits, integrating
 system shall connect such counter to lower bits of 
\series bold
\shape italic
timestamp
\series default
\shape default
 input, and drive unused high bits to zero.
 Integrating system shall also set 
\series bold
\shape italic
active_timestamp_bits 
\series default
\shape default
to width of such counter - 1 (e.g.
 when system has 32 bit timestamp, it shall be connected to 
\series bold
\shape italic
timestamp[31:0]
\series default
\shape default
 and 
\series bold
\shape italic
active_timestamp_bits=
\series default
\shape default
31).
\end_layout

\begin_layout Section
Clock and reset
\begin_inset CommandInset label
LatexCommand label
name "sec:Clock-and-reset"

\end_inset


\end_layout

\begin_layout Standard
CTU CAN FD is clocked via single clock input which represents System clock
 domain.
 Name of clock signal is different depending on used memory bus wrapper
 as is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:clock-signal-names"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 CTU CAN FD has single external reset which is treated as asynchronous reset,
 and it is internally synchronized by reset synchronizer (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Reset-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 Note that AHB bus specifications requires 
\series bold
\shape italic
hresetn 
\series default
\shape default
to be synchronous to 
\series bold
\shape italic
hclk
\series default
\shape default
.
 CTU CAN FD implemenation is more relaxed, and does not require these signals
 to be synchronous to 
\series bold
\shape italic
hclk
\series default
\shape default
 (System clock), since it handles reset synchronisation internally.
 
\series bold
\shape italic
res_n_out
\series default
\shape default
 signal output contains synchronized version of 
\series bold
\shape italic
res_n
\series default
\shape default
/
\series bold
\shape italic
arstn/hresetn
\series default
\shape default
 input.
 It can be left unconnected, or it can be used as an indication that reset
 has been completed and CTU CAN FD can be accessed on its memory bus.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="30.5line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="30line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Clock signal name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reset signal name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RAM-like
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sys_clk
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
res_n
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
APB
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
aclk
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
arstn
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
AHB
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hclk
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
hresetn
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Clock signal names
\begin_inset CommandInset label
LatexCommand label
name "tab:clock-signal-names"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Test probe
\end_layout

\begin_layout Standard
CTU CAN FD contains 
\series bold
\shape italic
test_probe
\series default
\shape default
 record output.
 This signal is used by CTU CAN FD test-bench to peek inside the design
 of CTU CAN FD.
 When integrating CTU CAN FD, this output can remain un-connected.
 Reffer to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-5"
literal "false"

\end_inset

 for description of how to connect test-probe if integrating CTU CAN FD
 VIP.
 This signal has no effect on design functionality, and it can remain unconnecte
d in design to which CTU CAN FD is integrated.
\end_layout

\begin_layout Section
Scan enable
\begin_inset CommandInset label
LatexCommand label
name "sec:Scan-enable"

\end_inset


\end_layout

\begin_layout Standard
CTU CAN FD design is DFT insertion friendly.
 When 
\series bold
\shape italic
scan_enable
\series default
\shape default
 = 1, CTU CAN FD is in scan mode.
 In scan mode, the following is valid:
\end_layout

\begin_layout Itemize
All hand-instantiated clock gates in CTU CAN FD are un-gated (to make sure
 that scan chain is always clocked).
\end_layout

\begin_layout Itemize
All resets which depend on value of other flip-flops are gated (to avoid
 reseting part of scan chain during scan operation).
\end_layout

\begin_layout Standard

\series bold
\shape italic
scan_enable
\series default
\shape default
 input shall be controlled by SoC level DFT controller, and it shall be
 connected to the same signal which enables scan mode on inserted scan flip-flop
s.
 If CTU CAN FD is used in FPGA (
\series bold
\shape italic
target_technology
\series default
\shape default
 = 1), 
\series bold
\shape italic
scan_enable
\series default
\shape default
 shall be tied low.
 
\series bold
\shape italic
scan_enable
\series default
\shape default
 signal shall be driven synchronous to System clock.
\end_layout

\begin_layout Section
Configuration options
\end_layout

\begin_layout Standard
CTU CAN FD is configurable on top level interface via VHDL generics which
 are explained in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:CAN-generics"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="13" columns="5">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="47text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Default
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Range
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
rx_buf_size
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
natural
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
128
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32-4096
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Size of RX buffer RAM in 32 bit words.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:RX-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
txt_buffer_count
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
natural
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2-8
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Number of TXT buffers.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:TXT-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_filt_A
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synthesize filter A.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Frame-Filters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_filt_B
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synthesize filter B.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Frame-Filters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_filt_C
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synthesize filter C.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Frame-Filters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_range
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synthesize range filter.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Frame-Filters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_traffic_counters
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synthesize traffic counters.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Bus-traffic-counters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
target_technology
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
natural
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0-1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Target technology (set 0 for ASIC, set 1 for FPGA).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_test_registers
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synthesize test registers.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
sup_parity
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
false
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Add parity protection to TXT buffers / RX buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
reset_buffer_rams
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
false
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
true/false
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When true, TXT buffer and RX buffer RAMs are reset by 
\series bold
\shape italic
res_n
\series default
\shape default
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
active_timestamp_bits
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
integer
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
63
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0-63
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Number of active timestamp bits minus - 1.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
CTU CAN FD generic parameters
\begin_inset CommandInset label
LatexCommand label
name "tab:CAN-generics"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Chapter
System architecture
\end_layout

\begin_layout Section
Block diagram
\end_layout

\begin_layout Standard
Detailed block diagram of CTU CAN FD IP Core is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:CTU-CAN-FD-Block-diagam"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_IP_Core_system.pdf
	lyxscale 20
	scale 50

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
CTU CAN FD - Detailed block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:CTU-CAN-FD-Block-diagam"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Reset architecture
\end_layout

\begin_layout Standard
CTU CAN FD IP Core can be reset by two means: External reset and Soft Reset.
 Both reset sources are described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:reset-description"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Both reset cause assertion of internal System reset which resets whole
 CTU CAN FD including Memory registers.
 Reset architecture is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:reset-structure"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 An example of reset sequence by both External and Soft reset are shown
 in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Reset-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Note that all DFFs in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:reset-structure"
plural "false"
caps "false"
noprefix "false"

\end_inset

 are clocked by System clock.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15text%">
<column alignment="left" valignment="top" width="25text%">
<column alignment="left" valignment="top" width="52text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reset Name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Asserted by
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reset description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
External Reset
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RAM like interface:
\series bold
\shape italic

\begin_inset Newline newline
\end_inset

res_n
\series default
\shape default
 = 0.
 
\end_layout

\end_inset
</cell>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
To be used by HW reset structure integrating CTU CAN FD (e.g.
 POR, System level reset controller).
 CTU CAN FD shall not be accessed for two System clock periods after External
 reset was de-asserted (or until 
\series bold
\shape italic
res_n_out
\series default
\shape default
 = 1).
 Asserting External reset does not require System clock to be running.
 De-asserting reset requires System clock to be running.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
AHB interface: 
\series bold
\shape italic

\begin_inset Newline newline
\end_inset

hresetn
\series default
\shape default
 = 0.
\end_layout

\end_inset
</cell>
<cell multirow="4" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
APB interface:
\series bold
\shape italic
 
\begin_inset Newline newline
\end_inset

aresetn
\series default
\shape default
 = 0.
\end_layout

\end_inset
</cell>
<cell multirow="4" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Soft Reset
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Writing MODE[RST] = '1'.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
To be used by SW for resetting CTU CAN FD.
 System clock must be running when this reset is asserted (needed for Bus
 access and pipeline DFF).
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Reset description
\begin_inset CommandInset label
LatexCommand label
name "tab:reset-description"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/Reset_structure.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Reset structure
\begin_inset CommandInset label
LatexCommand label
name "fig:reset-structure"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/reset_sequence.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Reset operation
\begin_inset CommandInset label
LatexCommand label
name "fig:Reset-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Clock architecture
\end_layout

\begin_layout Standard
CTU CAN FD IP Core contains one clock domain: System clock.
 There are no divided clocks in CTU CAN FD, thus no 
\begin_inset Quotes eld
\end_inset

generated clocks
\begin_inset Quotes erd
\end_inset

 are needed when writing SDC constraints.
 All timing related information (e.g.
 
\color red
time quanta
\color inherit
) are derived from System clock via clock enable signals.
 This makes CTU CAN FD fully synchronous design with no clock domain crossing.
 
\end_layout

\begin_layout Standard
CTU CAN FD is assumed to be implemented in a single power domain, all parts
 of CTU CAN FD must be either turned on or off.
 To reduce dynamic power consumption, majority of registers are written
 to allow usage of 
\begin_inset Quotes eld
\end_inset

clock enables
\begin_inset Quotes erd
\end_inset

 (FPGAs) or inferred 
\begin_inset Quotes eld
\end_inset

clock gating
\begin_inset Quotes erd
\end_inset

 (ASIC).
\end_layout

\begin_layout Standard
If 
\series bold
\shape italic
target_technology
\series default
\shape default
 = 0 (ASIC), hand-written clock gating is implemented for Memory registers,
 RX buffer RAM and TXT buffer RAMs.
 If 
\series bold
\shape italic
target_technology
\series default
\shape default
 = 1 (FPGA), no hand-written clock gating is implemented, clocks for memory
 registers RX buffer RAMs , and TXT buffer RAMs are always enabled.
 There is no functional difference between ASIC/FPGA target technology (even
 if clocks are always enabled, registers are wrriten only when enabled).
\end_layout

\begin_layout Standard
The manually used clock gating cell (clk_gate.vhd) has Latch + AND type.
 It is recommended to replace clk_gate with with Integrated clock gating
 cell by rewriting content of clk_gate.vhd.
\end_layout

\begin_layout Standard
If 
\series bold
\shape italic
target_technology
\series default
\shape default
 = 1 (FPGA), then clk_gate.vhd does not gate clocks, but only connects input
 clock to output clock.
\end_layout

\begin_layout Standard
If CTU CAN FD is implemented in SoC system, it is recommended to implement
 configurable clock gating for whole CTU CAN FD peripheral on system level
 to save power when CTU CAN FD is not clocked.
 In such situation, CTU CAN FD ignores traffic on CAN Bus, and continously
 transmitts 
\color red
recessive
\color inherit
 bits to CAN Bus.
\end_layout

\begin_layout Section
Testability
\end_layout

\begin_layout Standard
CTU CAN FD contains following features for manufacturing testability:
\end_layout

\begin_layout Enumerate
Memory testability - Allows direct read/write access to TXT buffer RAMs
 and RX buffer RAM.
 This approach is supported only when Test registers memory region is synthesize
d (
\series bold
\shape italic
sup_test_registers
\series default
\shape default
 = true).
 It is recommended to synthesize Test registers only for ASIC implementations
 (
\series bold
\shape italic
target_technology
\series default
\shape default
 = 0).
 Enabling Test registers for FPGA implementations is usefull only to test
 parity protection of RX / TXT buffer RAMs, since access from Test Registers
 bypasses parity encoding mechanism.
\end_layout

\begin_layout Enumerate
Scan mode (via 
\series bold
\shape italic
scan_enable
\series default
\shape default
 input) - In scan mode, all clock gates are enabled, and all reset signals
 which depend on other signals (generated reset) are gated.
\end_layout

\begin_layout Subsection
Memory testability
\end_layout

\begin_layout Standard
Each memory within CTU CAN FD can be tested at production via Test Registers
 (e.g.
 executing SW driven march pattern test).
 Any data can be written to any address inside each memory.
 Memory testability is available only in Test Mode (MODE[TSTM] = 1).
 If CTU CAN FD is not in Test mode, accesses to whole Test registers block
 are ignored.
 Memory testability has its own 
\begin_inset Quotes eld
\end_inset

enable
\begin_inset Quotes erd
\end_inset

 bit (TSTCTRL[TMENA]), which must be set to enable memory testing via Test
 Registers.
 An example of memory testing is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:memory-testability-example"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Note that this test sequence is only an example.
 Since Test registers provide independed Read/Write functionality to arbitrary
 addresses, any known testing approach can be used (any address step, direction
 or data pattern can be used).
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="11" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set MODE[TSTM] = 1 and TSTCTRL[TMENA] = 1.
 This enables memory testing.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Configure target memory to be tested in TST_DEST[TST_MTGT] register.
 Set TST_DEST[TST_ADDR] = 0 (initial address).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write test pattern to TST_WDATA register.
 It is up to user to choose test pattern.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Execute write to the memory by writing TSTCTRL[TWRSTB] = 1.
 Note that TSTCTRL[TMAENA] must remain set.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Increment address in TST_DEST[TST_ADDR].
 If this is last address within tested memory, then go to Step 6.
 Otherwise go to Step 3.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set TST_DEST[TST_ADDR] = 0 (initial address).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Wait for 1 System clock clock cycle (read from RAMs is pipelined).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read value from TST_RDATA.
 Check that value read from this register matches what has been written
 TST_WDATA register in Step 3.
 If value does not match, test fails.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Increment address in TST_DEST[TST_ADDR].
 If this is last address within tested memory, then go to Step 10.
 Otherwise go to Step 7.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Test is successfull\SpecialChar endofsentence

\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Memory testing example
\begin_inset CommandInset label
LatexCommand label
name "tab:memory-testability-example"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Sequential logic
\end_layout

\begin_layout Standard
CTU CAN FD logic is implemented from DFFs with asynchronous reset.
\end_layout

\begin_layout Standard
TXT buffer and RX buffer RAMs (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Memories"
plural "false"
caps "false"
noprefix "false"

\end_inset

) are by default implemented from DFFs.
 All DFFs are active on positive clock edge.
 CTU CAN FD is latch free (apart from latches within clock gate cells).
 These facts can be used as a sanity check that there should be no DFFs
 without Set and Reset within CTU CAN FD after synthesis (apart from TXT
 buffer / RX buffer RAMs, if they are synthesized, not inferred, nor replaced
 by Hard RAM macros).
\end_layout

\begin_layout Section
Resynchronisers
\end_layout

\begin_layout Standard
Resynchronisers within CTU CAN FD IP Core are listed in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:Resynchronisers-list"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="30text%">
<column alignment="left" valignment="top" width="20text%">
<column alignment="left" valignment="top" width="42text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Resynchroniser function
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Resynchroniser Type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Resynchroniser path
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Resynchronisation of External Reset
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reset Synchroniser
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
can_top_level
\backslash
rst_sync_inst
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Resynchronisation of CAN RX Data Stream
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal Synchroniser
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
can_top_level
\backslash
 bus_sampling_inst
\backslash
 can_rx_sig_sync_inst
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Resynchronisers
\begin_inset CommandInset label
LatexCommand label
name "tab:Resynchronisers-list"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Memories
\begin_inset CommandInset label
LatexCommand label
name "sec:Memories"

\end_inset


\end_layout

\begin_layout Standard
CTU CAN FD contains memories which are used to store CAN FD frames.
 These memories are parts of RX buffer and TXT buffers (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:RX-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:TXT-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 List of memories is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:RAM-memories"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 The TXT buffers and RX buffers can be either with or without reset:
\end_layout

\begin_layout Itemize
If 
\series bold
\shape italic
reset_buffer_rams
\series default
\shape default
 = false, TXT buffer RAMs and RX buffer RAM are not reset.
\end_layout

\begin_deeper
\begin_layout Itemize
The memories initialize to X.
\end_layout

\begin_layout Itemize
On FPGA, SRAM / BRAM blocks are inferred.
\end_layout

\begin_layout Itemize
On ASIC, DFT insertion may be complicated since DFFs of TXT buffer and RX
 buffer RAM are not controllable.
\end_layout

\begin_layout Itemize
ASIC fault-coverage can be achieved by functional test via Test Registers.
\end_layout

\end_deeper
\begin_layout Itemize
If 
\series bold
\shape italic
reset_buffer_rams
\series default
\shape default
 = true, TXT buffer RAMs and RX buffer RAM are reset.
\end_layout

\begin_deeper
\begin_layout Itemize
The memories initialize to 0.
\end_layout

\begin_layout Itemize
On FPGA, SRAM / BRAM blocks will not be inferred.
\end_layout

\begin_layout Itemize
On ASIC, DFT insertion is easy since DFFs of TXT buffer and RX buffer are
 as any other registers.
\end_layout

\begin_layout Itemize
ASIC fault coverage can be achieved by DFT + ATPG, no need to synthesize
 Test Registers.
\end_layout

\end_deeper
\begin_layout Standard
When integrating CTU CAN FD to ASIC, integrator can either replace these
 memories by hard macros, or leave memory implementation to synthesis tool.
 In such case, memory is synthesized from DFFs.
\end_layout

\begin_layout Standard
Each memory is synchronous memory with one clock cycle latency on data read,
 and one cycle write access latency.
 Both memories are dual port memories with write-only port A, read-only
 port B, and the same clock signal is used to clock both ports.
 If true dual port memories are used, write data/enable of Port B shall
 be driven to 0.
 Memory word width is 32 bits, and it must support byte-enable capability.
 An example of memory access is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:dual-port-RAM-access"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 In case of read during write, memories return old data value, there is
 no 
\begin_inset Quotes eld
\end_inset

bypassing
\begin_inset Quotes erd
\end_inset

 implemented.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="10">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="6page%">
<column alignment="left" valignment="top" width="0.8cm">
<column alignment="left" valignment="top" width="2.4cm">
<column alignment="left" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="6.5line%">
<column alignment="left" valignment="top" width="1cm">
<column alignment="left" valignment="top" width="1.1cm">
<column alignment="left" valignment="top" width="1.1cm">
<column alignment="left" valignment="top" width="1.1cm">
<column alignment="left" valignment="top" width="0pt">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory location
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Write mask
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Instance Name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Instances
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Depth
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Word Width
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Address size
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Port A Access
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Port B Access
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX buffer RAM
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
rx_buffer_ram
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32-
\end_layout

\begin_layout Plain Layout
4096
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5-12
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN Core
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory Registers
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synchronous
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer RAM
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
txt_buffer_ram
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2-8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
20
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory registers
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN Core
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synchronous
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RAM memories
\begin_inset CommandInset label
LatexCommand label
name "tab:RAM-memories"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/dual_port_mems.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Dual port memories access
\begin_inset CommandInset label
LatexCommand label
name "fig:dual-port-RAM-access"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Pipeline architecture and triggers
\end_layout

\begin_layout Standard
Processing of data on CAN bus in CTU CAN FD is pipelined into three stages
 which are described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:pipeline-stages-description"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 This architecture meets maximal 
\color red
information processing time
\color inherit
 when System clock is equal to 
\color red
time quanta
\color inherit
 (prescaler is 1).
 Since processing takes two clock periods 
\color red
information processing time
\color inherit
 of CTU CAN FD is 2.
 Due to this, 
\color red
minimum time quanta
\color inherit
 of CTU CAN FD is 1.
\end_layout

\begin_layout Standard
Each stage of pipeline processing is controlled by a trigger signal which
 is active for one clock cycle.
 Trigger signals are used to synchronise data transfer in exact moments
 to meet bit timing requirements on CAN Bus.
 Trigger signals are used as clock enable signals for DFF which processes
 data in according pipeline stage.
 If a trigger signal is inactive, processed data remain on DFF output and
 keep their previous value (data after bit destuffing (RX) and bit stuffing
 (TX)).
 An example of pipeline processing is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:data-path-pipeline"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Note that Process pipeline stage always occurs one clock cycle after Destuff
 pipeline stage.
 Between Process and Stuff pipeline stage there will be number of clock
 cycles where no data are processed.
 This gap corresponds to TSEG2 (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Bit-Rate-configuration"
plural "false"
caps "false"
noprefix "false"

\end_inset

 for definition of TSEG2).
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/pipeline_example.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Datapath pipeline processing
\begin_inset CommandInset label
LatexCommand label
name "fig:data-path-pipeline"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
In case of 
\color red
negative resynchronisation
\color inherit
, length of TSEG2 can be shortened to less then 2 clock cycles.
 In such case, following TX Trigger signal is throttled by one clock cycle
 and overall length of bit remains unaffected.
 Such situation is further described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Trigger-generator"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 A high level algorithm for processing of data on CAN bus is described in
 Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:pipeline-stages-algorithm"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="6">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="20line%">
<row>
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\begin_inset Text

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Index
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pipeline stage
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Trigger signal
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Corresponding moment on CAN Bus
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Modules which process data in this pipeline stage
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX Trigger (0)
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Sample point
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus Sampling, Bit Destuffing
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff Bits are removed from 
\series bold
\shape italic
can_rx 
\series default
\shape default
and destuffed data are provided to Protocol control.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX Trigger (1)
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
One clock cycle after Sample point
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol Control
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuffed data are processed by Protocol control, value of following transmitted
 bit is determined and provided as TX data before bit stuffinh.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Start of Bit time
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit Stuffing
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff bit is inserted to TX data before bit stuffing and propagated to 
\series bold
\shape italic
can_tx
\series default
\shape default
.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Pipeline stages
\begin_inset CommandInset label
LatexCommand label
name "tab:pipeline-stages-description"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="11" columns="4">
<features islongtable="true" longtabularalignment="center">
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<column alignment="left" valignment="top" width="62line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="15line%">
<row>
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\begin_inset Text

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Step
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pipeline Stage
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Module
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
can_rx
\series default
\shape default
 input is synchronised to System clock domain.
 Delay imposed by synchronisation is treated as wire delay and it is ignored.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus value is sampled to save information about previous sampled bus value
 for next edge detection.
 Synchronisation edges are detected on 
\series bold
\shape italic
can_rx
\series default
\shape default
 and propagated to Prescaler.
 
\series bold
\shape italic
can_rx
\series default
\shape default
 value is propagated to Bit Destuffing module.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus Sampling
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Bit de-stuffing
\color inherit
 is performed in 
\color red
Sample point
\color inherit
, and destuffed data are provided on output of Bit Destuffing module.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit Destuffing
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC from RX bit value with stuff bits included (
\series bold
\shape italic
can_rx
\series default
\shape default
) is calculated.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN CRC
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuffed data are sampled by Protocol control, RX shift register is shifted,
 TX shift register is preloaded by following bit to be transmitted, Protocol
 control FSM state is updated.
 
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol Control
\end_layout

\end_inset
</cell>
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC from destuffed data is calculated.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN CRC
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Stuff bits
\color inherit
 are inserted to TX bit value on output of TX shift register by Bit Stuffing
 module.
 Value on output of Bit Stuffing module is propagated to 
\series bold
\shape italic
can_tx
\series default
\shape default
 output.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit Stuffing
\end_layout

\end_inset
</cell>
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<row>
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\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX shift register is shifted.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol Control
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC from output of TX shift register (TX data before 
\color red
bit stuffing
\color inherit
) is calculated.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN CRC
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC from TX data with 
\color red
bit stuffing
\color inherit
 is calculated.
 As this stage does not affect data transmitted on the bus in the actual
 bit, it is not considered as separate pipeline stage.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff + 1 clock cycle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN CRC
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Pipeline stages - algorithm
\begin_inset CommandInset label
LatexCommand label
name "tab:pipeline-stages-algorithm"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
CAN Frame metadata
\end_layout

\begin_layout Standard
Through this document, term 
\begin_inset Quotes eld
\end_inset

CAN frame metadata
\begin_inset Quotes erd
\end_inset

 is used to describe information shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:CAN-frame-metadata"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 In TXT buffers and RX buffer, metadata are stored in Frame Format word
 as is shown in Chapter 4 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

.
\end_layout

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\noindent
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<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="20text%">
<column alignment="left" valignment="top" width="42text%">
<row>
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Name
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\backslash
cellcolor{gray}
\end_layout

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\end_layout

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</cell>
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Abbreviation
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\backslash
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\end_layout

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\end_layout

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</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

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Possible values 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Identifier type
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ID_TYPE
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BASE (0), EXTENDED (1)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Distiguishes frames with 
\color red
base identifier
\color inherit
 (BASE) only and frames with 
\color red
identifier extension
\color inherit
 (EXTENDED).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame type
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FR_TYPE
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
NORMAL_CAN (0), FD_CAN (1)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Distiguishes CAN 2.0 frames and CAN FD frames.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Remote Transmission Request
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RTR
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
NO_RTR_FRAME (0), RTR_FRAME (1)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Distinguishes between 
\color red
Data Frame
\color inherit
 and 
\color red
Remote frame
\color inherit
.
 When frame is CAN FD frame, RTR bit has no meaning.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit Rate Shift flag
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BRS
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BR_NO_SHIFT (0), BR_SHIFT (1)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Distinguishes if 
\color red
bit rate
\color inherit
 will be shifted in CAN FD frame or not.
 This bit has no meaning in CAN 2.0 frames.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error State Indicator
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ESI
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ESI_ERR_ACTIVE (0), ESI_ERR_PASSIVE (1)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Value of received 
\color red
ESI
\color inherit
 bit.
 This bit has no meaning in CAN 2.0 frames.
 This bit has no meaning in TXT buffers.
 Value of transmitted 
\color red
ESI
\color inherit
 bit is always given by actual 
\color red
Fault confinement state
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data length code
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
DLC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0 - 15 as defined in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data length code
\color inherit
 determines length of 
\color red
data field
\color inherit
 within CAN frame.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
CAN frame metadata
\begin_inset CommandInset label
LatexCommand label
name "tab:CAN-frame-metadata"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
CAN Frame format
\begin_inset CommandInset label
LatexCommand label
name "sec:CAN-frame-format"

\end_inset


\end_layout

\begin_layout Standard
CAN frame spans multiple 32-bit words in TXT buffers and within RX buffer
 RAMs (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:TXT-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:RX-Buffer"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 One TXT buffer always contains single frame.
 RX buffer contains multiple frames one after another in a RX buffer RAM.
 Format of CAN frame within these memories is the same with following exceptions
:
\end_layout

\begin_layout Itemize

\color red
ESI
\color inherit
 bit in TXT buffer has no meaning while in RX buffer ESI has value of received
 
\color red
ESI
\color inherit
 bit on CAN bus
\end_layout

\begin_layout Itemize
RWCNT field in TXT buffer has no meaning while in RX buffer it contains
 number of words that current frame takes in RX buffer without Frame Format
 word).
\end_layout

\begin_layout Itemize
FRAME_TEST_W word is available only in TXT buffer RAM, not in RX buffer
 RAM.
\end_layout

\begin_layout Standard
Meaning of memory words within CAN frame is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:CAN-frame-format-memory-words"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Meaning of individual bits can be found in Chapter 5 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15text%">
<column alignment="left" valignment="top" width="17text%">
<column alignment="left" valignment="top" width="60text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Name of memory word
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Name in register map (see 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

)
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame Format
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FRAME_FORM_W
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Contains CAN frame metadata and additional per-frame information.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Identifier
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
IDENTIFIER_W
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Contains 
\color red
base identifier
\color inherit
 base and 
\color red
identifier extension
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamp Low
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TIMESTAMP_L_W
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Contains lower 32-bits of CAN frame Timestamp (in RX buffer as sampled during
 frame reception, in TXT buffer as inserted by user).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamp High
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TIMESTAMP_U_W
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Contains upper 32-bits of CAN frame Timestamp (in RX buffer as sampled during
 frame reception, in TXT buffer as inserted by user).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data words
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
DATA_X_Y_W
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Contain CAN frame data payload transmitted/received during 
\color red
data frame
\color inherit
 field.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame Test
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FRAME_TEST_W
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Contains metadata for intentional corruption of transmitted CAN frames.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
CAN frame format - memory words
\begin_inset CommandInset label
LatexCommand label
name "tab:CAN-frame-format-memory-words"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Test mode
\end_layout

\begin_layout Standard
CTU CAN FD is in Test mode when MODE[TSTM] = '1'.
 Features of test mode are listed in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:test-mode-features"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="10text%">
<column alignment="left" valignment="top" width="82text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Relevant register
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTR_PRES
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTR_PRES is writable and allows setting values of 
\color red
transmitt error counter
\color inherit
, 
\color red
receive error counter
\color inherit
, nominal error counter and data error counter.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
EWL
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
EWL register is read-write therefore Error warning limit is configurable
 by SW.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ERP
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ERP register is read-write and Error passive threshold is configurable by
 SW.
 When either
\color red
 transmitt error counter
\color inherit
 or 
\color red
receive error counter
\color inherit
 reaches Error Passive threshold, unit becomes 
\color red
error passive
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TST_CONTROL, TST_DEST, TST_WDATA, TST_RDATA
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Test registers are writable, therefore it is possible to directly read/write
 RX buffer RAM and TXT buffer RAMs.
 This feature is available only when 
\series bold
\shape italic
sup_test_registers
\series default
\shape default
 = true.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FRAME_TEST_W
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTU CAN FD uses bits in FRAME_TEST_W to intentionally corrupt transmitted
 CAN frames.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Test mode features
\begin_inset CommandInset label
LatexCommand label
name "tab:test-mode-features"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Integration vs.
 Reintegration
\end_layout

\begin_layout Standard
In this document term 
\begin_inset Quotes eld
\end_inset

Integration
\begin_inset Quotes erd
\end_inset

 means attempt to detect 11 consecutive 
\color red
recessive
\color inherit
 bits after logic 1 was written to SETTINGS[ENA] (CTU CAN FD was turned
 on).
 Term 
\begin_inset Quotes eld
\end_inset

Reintegration
\begin_inset Quotes erd
\end_inset

 means attempt to detect 129 ocurrences of 11 consecutive recessive bits
 after node went 
\color red
bus off
\color inherit
 and logic 1 was written to COMMAND[ERCRST] (SW Requests to rejoin the bus).
\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Chapter
Sub-blocks architecture
\end_layout

\begin_layout Section
CAN Core
\end_layout

\begin_layout Description
File: can_core.vhd
\end_layout

\begin_layout Standard
CAN core block diagram is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:CAN-Core-Block-diagam-1"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 CAN core is structural entity that instantiates other modules and by itself
 it implements nearly no logic.
 An exception to this rule are two multiplexers as shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:CAN-Core-Block-diagam-1"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Multiplexor on TX datapath (green color) multiplexes between transmitted
 data after 
\color red
bit stuffing
\color inherit
 or constant 
\color red
recessive
\color inherit
 value.
 Constant 
\color red
recessive
\color inherit
 value is sent to the bus in 
\color red
bus monitoring mode
\color inherit
.
 Multiplexor on RX datapath (red color) multiplexes input data to Bit destuffing
 module.
 During normal operation, 
\series bold
\shape italic
can_rx
\series default
\shape default
 input is used.
 When 
\color red
secondary sample point
\color inherit
 is used, data after 
\color red
bit stuffing
\color inherit
 are taken (transmitted data are looped back to make sure that Protocol
 control FSM receives proper value as real received value can be delayed
 by several bits).
 In 
\color red
bus monitoring mode
\color inherit
, data afer 
\color red
bit stuffing
\color inherit
 are logically ORed with 
\series bold
\shape italic
can_rx
\series default
\shape default
 from input of CAN core (this corresponds to re-routing transmitted bit
 value internally as defined in 10.14 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

).
 
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_CAN_Core.pdf
	lyxscale 20
	scale 60

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
CAN Core - Block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:CAN-Core-Block-diagam-1"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsection
Protocol control
\end_layout

\begin_layout Description
File: protocol_control.vhd
\end_layout

\begin_layout Standard
Protocol control diagram is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Protocol-Control-Block-diagam"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Protocol control is structural entity thah only instantiates other modules
 and by itself it implements no logic.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_Protocol_control.pdf
	lyxscale 20
	scale 57

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Protocol control - Block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:Protocol-Control-Block-diagam"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsubsection
Protocol control FSM
\end_layout

\begin_layout Description
File: protocol_control_fsm.vhd
\end_layout

\begin_layout Standard
Protocol control FSM implements following functionality:
\end_layout

\begin_layout Itemize
Transmits and receives CAN frames.
\end_layout

\begin_layout Itemize
Controls Control counter, Retransmitt Counter, Re-integration counter.
\end_layout

\begin_layout Itemize
Controls TX Shift Register.
\end_layout

\begin_layout Itemize
Controls RX Shift Register.
 Storing values from RX Shift register to RX buffer.
\end_layout

\begin_layout Itemize
Reads transmitted frame from TXT buffer (addressing and reading data words
 from TXT buffer).
\end_layout

\begin_layout Itemize
Stores received frame to RX buffer.
\end_layout

\begin_layout Itemize
Controls measurement of 
\color red
transmitter delay
\color inherit
.
\end_layout

\begin_layout Itemize
Controls TXT buffers and TX Arbitrator via HW Commands.
\end_layout

\begin_layout Itemize
Controls 
\color red
synchronisation
\color inherit
 (no 
\color red
synchronisation
\color inherit
, 
\color red
hard synchronisation
\color inherit
, 
\color red
resynchronisation
\color inherit
)
\end_layout

\begin_layout Itemize
Controls 
\color red
bit rate
\color inherit
 
\color red
switching
\color inherit
 (Nominal Sample, Data Sample, Secondary Sample).
\end_layout

\begin_layout Itemize
Performs 
\color red
form error
\color inherit
 detection.
\end_layout

\begin_layout Itemize
Evaluates results of 
\color red
CRC check
\color inherit
.
\end_layout

\begin_layout Itemize
Handles 
\color red
arbitration
\color inherit
.
\end_layout

\begin_layout Standard
Protocol control FSM state transition diagam is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Protocol-control-FSM"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Rules for Protocol control FSM state transitions are described in Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:Protocol-control-state-transition-rules"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Protocol control FSM does not change its state in any other moment.
 The regular change of Protocol control FSM state corresponding to e.g.
 transition from 
\color red
control field
\color inherit
 to 
\color red
data field
\color inherit
 occurs one clock cycle after 
\color red
sample point
\color inherit
 (in Process pipeline stage).
 
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15text%">
<column alignment="left" valignment="top" width="17text%">
<column alignment="left" valignment="top" width="60text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Condition of state transition
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pipeline stage when transition occurs.
 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Regular condition
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transition corresponds to regular change of CAN frame field (e.g.
 
\color red
stuff count
\color inherit
 to 
\color red
CRC
\color inherit
).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error frame request
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
One clock cycle after Process
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transition corresponds to start of 
\color red
active error flag
\color inherit
 or 
\color red
passive error flag
\color inherit
 and can occur from any state of Protocol control FSM.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Protocol control state transition rules
\begin_inset CommandInset label
LatexCommand label
name "tab:Protocol-control-state-transition-rules"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_protocol_control.pdf
	lyxscale 20
	scale 95

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Protocol control FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:Protocol-control-FSM"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsubsection
Control counter
\end_layout

\begin_layout Description
File: control_counter.vhd
\end_layout

\begin_layout Standard
Control counter measures duration of CAN frame fields which last longer
 than 1 bit.
 These fields and according configuration of Control counter are shown in
 Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:CAN-control-counter"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Control counter counts towards zero.
 It is decremented by 1 in each bit of CAN frame field in Process pipeline
 stage.
 A current CAN frame field ends when Control counter is zero.
 Control counter is not counting during CAN frame fields which last only
 1 bit (e.g.
 
\color red
IDE
\color inherit
 bit), nor during fields which might last arbitrary number of bits (
\color red
bus idle
\color inherit
).
 An example of Control counter operation during 
\color red
base identifier
\color inherit
 in CAN frame is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:control-counter-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="14" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="47line%">
<column alignment="left" valignment="top" width="47line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN Frame field 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Control counter preload value
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base identifier
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Identifier extension
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
17
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data length code
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Depends on transmitted / received data field length.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
14, 16, 20 - depends on length of CRC sequence
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff count (+ Stuff parity)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
End of Frame
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Interframe space
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Suspend transmission
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Integration
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error flag, overload flag
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error delimiter, Overload delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Re-integration
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
11, preloaded 129 times.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Control counter
\begin_inset CommandInset label
LatexCommand label
name "tab:CAN-control-counter"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/control_counter.pdf
	lyxscale 20
	scale 90

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Control counter operation
\begin_inset CommandInset label
LatexCommand label
name "fig:control-counter-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Control counter module contains a complementary counter which counts from
 0.
 Complementary counter is incremented by 1 each bit time in Process pipeline
 stage and it counts only during 
\color red
data field
\color inherit
.
 Complementary counter provides information that data byte has elapsed (when
 counter mod 8 == 0), or whole memory word has elapsed (when counter mod
 32 == 0).
 Complementary counter addresses memory words between addresses 4 (DATA_1_4_W)
 and 19 (DATA_61_64_W) in TXT buffer.
 Complementary counter decodes address of Data memory word within TXT buffer
 according to following equation:
\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $Memory\,word\,index=\left(\frac{Control\,counter}{32}\right)+4$
\end_inset


\end_layout

\begin_layout Standard
Control counter module implements Arbitration lost capture register.
 Arbitration lost capture register stores position within CAN frame at which
 
\color red
arbitration
\color inherit
 was lost.
 Arbitration lost capture register is loaded when 
\color red
arbitration
\color inherit
 lost is signalled by Protocol Control FSM in Process pipeline stage.
 Arbitration lost capture saves current value of Control counter (determines
 bit at which 
\color red
arbitration
\color inherit
 was lost) and bit field type within arbitration (
\color red
base identifier
\color inherit
, 
\color red
IDE
\color inherit
 bit, 
\color red
identifier extension
\color inherit
, etc.) when arbitration was lost.
 Arbitration lost capture register is readable by SW via ALC register.
 Meaning of values in Arbitration lost capture register is described in
 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

.
 An example of Arbitration lost capture register is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:arbitration-lost-capture"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/arbitration_lost_capture.pdf
	lyxscale 20
	scale 90

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Arbitration lost capture 
\begin_inset CommandInset label
LatexCommand label
name "fig:arbitration-lost-capture"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsubsection
Retransmitt counter
\end_layout

\begin_layout Description
File: retransmitt_counter.vhd
\end_layout

\begin_layout Standard
Retransmitt counter controls number of 
\color red
retransmissions
\color inherit
 of a single CAN frame from a single TXT buffer.
 Retransmitt counter counts from zero, and it counts only when retransmitt
 limitation is enabled by user (SETTINGS[RTRLE] = '1').
 When retransmitt limitation is disabled (SETTINGS[RTRLE] = '0') CAN frame
 transmission is attempted indefinitely.
 Retransmitt counter is incremented by 1 when 
\color red
arbitration
\color inherit
 is lost, or when 
\color red
error frame
\color inherit
 transmission is requested by Error detector (reffer to 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Error-detector"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
\end_layout

\begin_layout Standard
When 
\color red
error frame
\color inherit
 and 
\color red
arbitration
\color inherit
 loss occur in the same frame, retransmitt counter is incremented only once
 (such a situation is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:retransmitt-counter-arbitration-loss"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 When multiple 
\color red
error frames
\color inherit
 occur in the same frame (e.g.
 due to error during 
\color red
error frame
\color inherit
), retransmitt counter is also incremented only once.
\end_layout

\begin_layout Standard
When Retransmitt counter reaches retransmitt limit (SETTINGS[RTRTH]), it
 signals this to Protocol control FSM.
 In case of next arbitration loss or 
\color red
error frame
\color inherit
 request, Protocol control FSM stops transmitting the actual frame and active
 TXT buffer moves to TX Failed state (see Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:txt-buffer-fsm"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 When unit is a receiver without attempt to transmitt a frame (no frame
 was available during 
\color red
bus idle
\color inherit
, 
\color red
intermission
\color inherit
), retransmitt counter is not modified during this frame.
 When unit is 
\color red
error passive
\color inherit
 and transmission of a frame is not succesfull, unit becomes 
\color red
receiver
\color inherit
 of next frame (due to 
\color red
suspend transmission
\color inherit
 field) without attempting to transmitt a frame.
 If error occurs during next frame, retransmitt counter is not incremented.
 Possible configurations of retransmitt limit are shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:retransmitt-counter-configurations"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
Retransmitt counter is cleared when TXT buffer used for transmission changes
 between two consecutive transmissions (another TXT buffer with another
 TX Frame selected by TX Arbitrator), as is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:txt-buffer-change"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Retransmitt counter is cleared upon succesfull transmission (TXT buffer
 goes to TX OK state) or when transmission fails (TXT buffer goes to TX
 Failed state).
 Retransmitt counter is also cleared when TXT buffer which is currently
 used for transmission goes to Aborted state.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="18text%">
<column alignment="left" valignment="top" width="17text%">
<column alignment="left" valignment="top" width="57text%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SETTINGS[RTRTH]
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SETTINGS[RTRLE]
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Behaviour
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame transmission is attempted without any limitation until unit turns
 Bus-off.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame transmission is attempted only once, there is no 
\color red
retransmission
\color inherit
 attempt after first failed transmission (so called one-shot mode).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1 - 15
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame transmission is attempted SETTINGS[RTRTH] times.
 
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Retransmitt limit configuration
\begin_inset CommandInset label
LatexCommand label
name "tab:retransmitt-counter-configurations"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/retransmitt_counter.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Retransmitt counter operation
\begin_inset CommandInset label
LatexCommand label
name "fig:retransmitt-counter"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/retransmitt_counter_arbitration.pdf
	lyxscale 20
	scale 61

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Retransmitt counter - arbitration loss and error frame 
\begin_inset CommandInset label
LatexCommand label
name "fig:retransmitt-counter-arbitration-loss"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/retransmitt_counter_OK.pdf
	lyxscale 20
	scale 61

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Retransmitt counter - second retransmission succesfull 
\begin_inset CommandInset label
LatexCommand label
name "fig:retransmitt-counter-OK"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsubsection*
Reintegration counter
\begin_inset CommandInset label
LatexCommand label
name "subsec:Reintegration-counter"

\end_inset


\end_layout

\begin_layout Description
File: reintegration_counter.vhd
\end_layout

\begin_layout Standard
Reintegration counter counts 129 consecutive ocurrences of 11 consecutive
 
\color red
recessive
\color inherit
 bits after CTU CAN FD turned 
\color red
bus-off
\color inherit
.
 Reintegration counter counts only during reintegration, not during initial
 
\color red
bus integration
\color inherit
.
 Reintegration counter counts from zero, and it is cleared when unit is
 
\color red
bus-off
\color inherit
 and it receives command to reset error counters (by writing logic 1 to
 COMMAND[ERCRST] register).
 Reintegration counter is incremented by 1 after each 11 consecutive 
\color red
recessive
\color inherit
 bits are received.
 11 consecutive recessive bits are measured by Control counter.
 If during 
\color red
reintegration
\color inherit
 dominant bit is detected, Control counter is pre-loaded again to 10 (there
 was 
\color red
dominant
\color inherit
 bit before 11 consecutive 
\color red
recessive
\color inherit
 bits were reached).
 When reintegration counter reaches 128 (0-128 = 129 times), it signals
 this to Protocol control FSM.
 Upon such event Protocol control FSM becomes Idle, unit becomes 
\color red
error active
\color inherit
 again and operation control state is changed to Idle.
 An example use case of reintegration counter operation is shown in Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:reintegration-counter"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="11" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="90line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTU CAN FD is enabled by writing SETTINGS[ENA] = '1'.
 After 
\color red
bus integration
\color inherit
 is over, unit becomes 
\color red
error active
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTU CAN FD takes part in bus communication.
 Due to 
\color red
error frames
\color inherit
, it turns first 
\color red
error passive
\color inherit
 and then 
\color red
bus-off
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW is notified of such an event by FCS interrupt, then SW reads FAULT_STATE
 register and finds out that unit is 
\color red
bus-off
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW decides that it wants the unit to join the network again.
 SW writes logic 1 to COMMAND[ERCRST] (so called 
\begin_inset Quotes eld
\end_inset

error counter reset
\begin_inset Quotes erd
\end_inset

 command or 
\begin_inset Quotes eld
\end_inset

reintegration request
\begin_inset Quotes erd
\end_inset

)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reintegration counter is cleared.
 Control counter is preloaded to 10.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Control counter is being decremented by 1 for each 
\color red
recessive
\color inherit
 bit received by Protocol Control FSM.
 If 
\color red
dominant
\color inherit
 bit is detected, Control counter is preloaded to 10 again.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
After 11 consecutive 
\color red
recessive
\color inherit
 bits are received, Control counter is 0, it signals this to Protocol control
 FSM.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM increments Reintegration counter by 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
After 129 repetitions of 11 consecutive 
\color red
recessive
\color inherit
 bits (note that there can be CAN frames between consecutive sequences of
 11 consecutive 
\color red
recessive
\color inherit
 bits, these frames are ignored by CTU CAN FD), Reintegration counter is
 128.
 Reintegration counter signals this to Protocol Control FSM.
 
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM becomes Idle, CTU CAN FD becomes 
\color red
error active
\color inherit
 and it is ready to receive/transmitt frames again.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Reintegration counter - use case
\begin_inset CommandInset label
LatexCommand label
name "tab:reintegration-counter"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsubsection*
TX shift register
\begin_inset CommandInset label
LatexCommand label
name "subsec:TX-Shift-Register"

\end_inset


\end_layout

\begin_layout Description
File: tx_shift_reg.vhd
\end_layout

\begin_layout Standard
TX shift register is 32 bit shift register which transmitts a bit sequence
 to the output of Protocol control module.
 TX shift register is preloaded by Protocol control FSM in Process pipeline
 stage when new data sequence is about to be transmitted, thus output value
 is also valid after Process pipeline stage of the same bit.
 TX shift register is shifted by one position in Stuff pipeline stage of
 each bit on CAN bus during multi-bit frame fields.
 When 
\color red
stuff bit
\color inherit
 is inserted, TX shift register is not shifted (Protocol control is halted
 for one bit).
\end_layout

\begin_layout Standard
TX shift register is preloaded according to Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-shift-reg-preload"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 TX shift register is enabled only as long as unit is 
\color red
transmitter
\color inherit
.
 TX shift register is not shifting when unit is 
\color red
receiver
\color inherit
, nor during CAN frame fields which last only one bit (
\color red
SOF
\color inherit
, 
\color red
ACK
\color inherit
, etc.), nor during fields which transmitt constant sequence (
\color red
EOF
\color inherit
, 
\color red
error flag
\color inherit
, etc.).
 In such case constant value is transmitted on its output.
 TX shift register shifts from lowest bit index to highest bit index (shifting
 up).
 Transmission of single bits (e.g.
 
\color red
SOF
\color inherit
, 
\color red
ACK
\color inherit
) or constant sequences (e.g.
 
\color red
active error flag
\color inherit
, EOF) is handled by separate logic inside TX shift register, and has higher
 priority than transmission from TX shift register.
 Rules for handling of these situations are described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-shift-reg-special-rules"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 An example of TX shift register operation during CAN frame is shown in
 Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-shift-reg-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="40line%">
<column alignment="left" valignment="top" width="22line%">
<column alignment="left" valignment="top" width="30line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN frame fields in which TX shift register is preloaded 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Preloaded bit sequence
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Where the bit sequence is preloaded from
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF
\color inherit
, 
\color red
suspend transmission
\color inherit
, 
\color red
intermission
\color inherit
, 
\color red
idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Base identifier
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Identifier capture register in TX Arbitrator.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
IDE
\color inherit
 bit
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Identifier extension
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Identifier capture register in TX Arbitrator.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
r0
\color inherit
 bit of CAN 2.0 frame with 
\color red
identifier extension
\color inherit
, 
\color red
EDL
\color inherit
/
\color red
r0
\color inherit
 bit.
 
\color red
ESI
\color inherit
 bit
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data length code
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Metadata capture registers in TX Arbitrator.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
data length code
\color inherit
, in 
\color red
data field
\color inherit
 when multiple of 32 bits of 
\color red
data field
\color inherit
 were transmitted.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data word (4 bytes) for transmission.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer RAM data output on Port B.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
data length code
\color inherit
 in ISO CAN FD frames without 
\color red
data field
\color inherit
, in last bit of 
\color red
data field
\color inherit
 in ISO CAN FD frames.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Stuff count
\color inherit
 and stuff parity.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Counter of stuffed bits in Bit Stuffing module.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
stuff count
\color inherit
, last bit of 
\color red
data field
\color inherit
 in non-ISO CAN FD frames (no 
\color red
stuff-count
\color inherit
), last bit of 
\color red
data length code
\color inherit
 in non-ISO CAN frames with no 
\color red
data field
\color inherit
.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Calculated CRC.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC calculation register in CAN CRC module.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX shift register preload rules
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-shift-reg-preload"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="47line%">
<column alignment="left" valignment="top" width="47line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit value transmitted 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Special conditon
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Dominant
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error frame request - unit is 
\color red
error active
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Recessive
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error frame request - unit is 
\color red
error passive
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Dominant
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM requests transmission of dominant bit
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Recessive
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX shift register is disabled and none of the above conditions apply.
 This situation corresponds to transmission of continuous stream of 
\color red
recessive
\color inherit
 bits.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX Shift register - special cases
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-shift-reg-special-rules"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="29" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="74line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN Frame:
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


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Data - Bit 8
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</lyxtabular>

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\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX shift register - example of operation
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-shift-reg-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsubsection*
RX shift register
\begin_inset CommandInset label
LatexCommand label
name "subsec:RX-Shift-Register"

\end_inset


\end_layout

\begin_layout Description
File: rx_shift_reg.vhd
\end_layout

\begin_layout Standard
RX shift register is 32 bit shift register which receives bit sequence and
 stores parts of this sequence to dedicated capture registers.
 RX shift register operates in two basic modes as is described in Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-shift-register-modes"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Mode of RX shift register determines whether input of each byte in shift
 register is taken from output of previous byte, or directly from input
 of RX shift register.
 Diagram of RX shift register is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-shift-reg-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Shifting of each byte of RX shift register is enabled separately and it
 is controlled by Protocol control FSM.
 RX Shift register is shifting during multi-bit fields on CAN bus and it
 shifts by one position each bit in Process pipeline stage.
 This corresponds to reception of bit from CAN bus.
 RX shift register shifts up.
 RX shift register stores part of its content to either a dedicated capture
 register, or RX buffer memory as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-buffer-stored-sequences"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Received 
\color red
CRC sequence
\color inherit
 is not stored into any capture register and it is used for 
\color red
CRC check
\color inherit
 directly from RX shift register (
\color red
CRC frame field
\color inherit
 is the last field of CAN frame which is shifted into RX shift register,
 therefore after CRC frame field, CRC remains in RX shift register).
\end_layout

\begin_layout Standard
RX shift register is not used till the end of frame and its content remains
 stable.
 Other one bit metadata information are stored to dedicated capture registers
 directly from input of RX shift register in corresponding fields of CAN
 frame as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-buffer-stored-bits"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 An example of RX shift register operation is shown in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-shift-reg-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="4">
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<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="19line%">
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\begin_layout Plain Layout
RX Shift register mode
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
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Bit fields on CAN bus when mode is used.
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

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Byte which is enabled.
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
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Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
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Linear mode
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Base identifier
\color inherit
, 
\color red
identifier extension
\color inherit
, 
\color red
DLC
\color inherit
, 
\color red
CRC sequence
\color inherit
, 
\color red
Stuff count
\end_layout

\end_inset
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\begin_layout Plain Layout
All bytes are enabled.
\end_layout

\end_inset
</cell>
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\begin_inset Text

\begin_layout Plain Layout
Shift register forms single 32-bit shift register.
 Inputs of each next byte are connected to outputs of previous byte.
 All bits are shifted simultaneously.
\end_layout

\end_inset
</cell>
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<row>
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\begin_layout Plain Layout
Byte mode
\end_layout

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\begin_layout Plain Layout

\color red
Data field
\end_layout

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\begin_inset Text

\begin_layout Plain Layout
Only one byte is enabled at any time.
 Enabled byte is given by index of actually received 
\color red
data field
\color inherit
 byte on CAN bus.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Shift register forms 4 separate 8-bit shift registers.
 Inputs of each byte are connected to input of RX shift register.
 Only 1 shift register (one byte) is shifted at any time.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX shift register modes
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-shift-register-modes"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
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<features tabularvalignment="middle">
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<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="30line%">
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\begin_layout Plain Layout
Bit on CAN bus in which
\end_layout

\begin_layout Plain Layout
RX shift register stores part of its content.
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
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Meaning of stored sequence 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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\begin_layout Plain Layout
Destination where value is stored.
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
base identifier
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Base identifier
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
identifier extension
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Extended identifier
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
data length code
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data length code
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
data field
\color inherit
 or last bit of memory word within 
\color red
data field
\color inherit
 (after each 32 bits).
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4 bytes (single memory word) of 
\color red
data field
\color inherit
.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX buffer RAM memory.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Last bit of 
\color red
stuff count
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Grey coded 
\color red
stuff count
\color inherit
 + 
\color red
stuff parity
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX shift register - stored sequences
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-buffer-stored-sequences"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="29line%">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="20line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM state
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Meaning of stored bit 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Corresponding metadata signal
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destination where value is stored.
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BRS
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Value of 
\color red
bit rate switch
\color inherit
 bit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BRS
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ESI
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Value of 
\color red
error state indicator
\color inherit
 bit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ESI
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
IDE
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Value of 
\color red
identifier extension
\color inherit
 bit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ID_TYPE
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RTR/SRR/R1, RTR/R1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Value of 
\color red
remote transmission request
\color inherit
 Bit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RTR
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
EDL/R0, EDL/R1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Value of 
\color red
extended data length
\color inherit
 / flexbile data-rate format bit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FR_TYPE
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture register
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX shift register - stored single bits
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-buffer-stored-bits"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_RX_Shift_reg.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX shift register - Block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-shift-reg-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="37" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="21.2line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="60line%">
<row>
<cell multicolumn="1" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN Frame:
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID: 0x123
\begin_inset Newline newline
\end_inset

DLC: 0x2
\begin_inset Newline newline
\end_inset

Data: 0xAB 0xCD
\begin_inset Newline newline
\end_inset

Frame Type: CAN FD Frame
\begin_inset Newline newline
\end_inset

Identifier Type: Base Identifier
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit on CAN bus
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Mode
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX shift Register status,
\begin_inset Newline newline
\end_inset

right most bit is received on input of Protocol control,
\begin_inset Newline newline
\end_inset

received sequence boldom
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SOF
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 00000000
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 0000000
\series bold
0
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 000000
\series bold
00
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 00000
\series bold
001
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 0000
\series bold
0010
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 000
\series bold
00100
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 00
\series bold
001001
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 7
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 0
\series bold
0010010
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000000 
\series bold
00100100
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 9
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 0000000
\series bold
0 01001000
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 10
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 000000
\series bold
00 10010001
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base ID - Bit 11
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000
\series bold
001 00100011 
\series default
(Base ID: 0x123: 00100100011)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RTR
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000001 00100011
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
IDE
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000001 00100011
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
r0
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000001 00100011
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
DLC - Bit 1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Linear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
00000000 00000000 00000010 0100011
\series bold
0
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
DLC - Bit 2
\end_layout

\end_inset
</cell>
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0000000 00000000 
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 10101011 (Data: 0xCD 1100 1101)
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</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX shift register operation
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-shift-reg-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsubsection
Error detector
\begin_inset CommandInset label
LatexCommand label
name "subsec:Error-detector"

\end_inset


\end_layout

\begin_layout Description
File: err_detector.vhd
\end_layout

\begin_layout Standard
Error detector processes errors detected by other modules, decides whether
 these errors are valid, and generates error frame request to Protocol control
 FSM.
 Errors are detected in Process pipeline stage, and error frame request
 is provided to Protocol control FSM one clock cycle after Process pipeline
 stage.
 Error frame request is registered to avoid combinatorial loops between
 Error detector and Protocol control FSM.
 Error types and modules of their origin are described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:Error-detection-rules-1"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Error detector containts Error code capture register which stores type
 and position of last error.
 Error code capture register is loaded when Error detector creates error
 frame request to Protocol control FSM.
 Reffer to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

 for description of Error code capture register.
 An example of error detection (
\color red
form error
\color inherit
) with details of actions in each pipeline stage is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:error-detector"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="5">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="5line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="8line%">
<column alignment="left" valignment="top" width="48line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
CAN frame fields when error is detected 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
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\begin_inset Text

\begin_layout Plain Layout
CAN Frame Fields where Error can't occur 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Module where error is detected
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
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\begin_inset Text

\begin_layout Plain Layout

\color red
Bit error
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF
\color inherit
, 
\color red
control
\color inherit
, 
\color red
data
\color inherit
, 
\color red
stuff count
\color inherit
, 
\color red
CRC
\color inherit
, 
\color red
CRC delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Can occur anywhere
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit error detector in Bus sampling module
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Bit error
\color inherit
 is detected when transmitted and received value of bit on CAN bus differs.
 Reffer to 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Bus-sampling"
plural "false"
caps "false"
noprefix "false"

\end_inset

 for details of 
\color red
bit error
\color inherit
 detection by Bus sampling module.
 
\color red
Bit error
\color inherit
 detection by Bus sampling module is enabled always, it is only ignored
 in bit fields as described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:Bit-error-exceptions"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
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<row>
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\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Arbitration field
\end_layout

\end_inset
</cell>
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\begin_inset Text

\begin_layout Plain Layout
Can occur anywhere
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
In 
\color red
arbitration field
\color inherit
, 
\color red
bit error
\color inherit
 detected by 
\color red
Bus sampling
\color inherit
 is ignored by Error detector.
 Instead 
\color red
bit error
\color inherit
 detected by Protocol control FSM is considered.
 Protocol control FSM detects 
\color red
bit error
\color inherit
 during 
\color red
arbitration field
\color inherit
 only when transmitted bit was 
\color red
dominant
\color inherit
 and received bit is 
\color red
recessive
\color inherit
.
\end_layout

\end_inset
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<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
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\end_layout

\end_inset
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\begin_inset Text

\begin_layout Plain Layout

\color red
Arbitration field
\color inherit
, 
\color red
control
\color inherit
, 
\color red
data
\color inherit
, 
\color red
stuff count
\color inherit
, 
\color red
CRC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Intermission
\color inherit
, 
\color red
idle
\color inherit
, 
\color red
suspend
\color inherit
, 
\color red
error frame
\color inherit
, 
\color red
overload frame
\color inherit
, 
\color red
end of frame
\color inherit
, 
\color red
CRC delimiter
\color inherit
, 
\color red
ACK
\color inherit
, 
\color red
ACK delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit destuffing module
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Stuff error
\color inherit
 is detected by Bit destuffing module as described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Bit-Destuffing"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 If 
\color red
fixed stuff bit
\color inherit
 does not have oposite value as previous bit, this error is detected as
 
\color red
stuff error
\color inherit
 by Bit destuffing module, but error is stored as 
\color red
form error
\color inherit
 in Error code capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Form error
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF
\color inherit
, 
\color red
control
\color inherit
, 
\color red
stuff count
\color inherit
, 
\color red
CRC
\color inherit
, 
\color red
EOF
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Arbitration
\color inherit
, 
\color red
data field
\color inherit
, 
\color red
ACK
\color inherit
, 
\color red
intermission
\color inherit
, 
\color red
suspend transmission
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM, Bit destuffing module for 
\color red
fixed stuff bits
\color inherit
.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Form error
\color inherit
 is detected by Protocol Control FSM by checking received bit during fixed
 frame fields as described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:Form-error-detection"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Protocol control signals 
\color red
form error
\color inherit
 to Error detector and based on this, Error frame request is signalled one
 clock cycle after Process pipeline stage.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Error detection rules (part 1)
\begin_inset CommandInset label
LatexCommand label
name "tab:Error-detection-rules-1"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="5">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="5line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="8line%">
<column alignment="left" valignment="top" width="48line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN frame fields when error is detected.
 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN frame fields where error can't occur.
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Module where error is detected
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
CRC error
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
ACK delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF, Arbitration, Control, Data, Stuff Count, CRC, CRC Delimiter, ACK, End
 of Frame, Intermission, Bus idle, Error frame, Overload frame
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Comparison of RX CRC with calculated CRC is executed in Error detector.
 After CRC field has passed, RX shift register is not shifting, and CRC
 module is not calculating CRC anymore, therefore comparison shows valid
 result from CRC delimiter further.
 Based on result of comparison 
\begin_inset Quotes eld
\end_inset

CRC match
\begin_inset Quotes erd
\end_inset

 is signalled to Protocol control FSM.
 If unit is 
\color red
receiver
\color inherit
 and 
\begin_inset Quotes eld
\end_inset

CRC match
\begin_inset Quotes erd
\end_inset

 is not signalled to Protocol control FSM in 
\color red
ACK delimiter
\color inherit
, Protocol control FSM detects 
\color red
CRC error
\color inherit
 (in Process pipeline stage of 
\color red
ACK delimiter
\color inherit
) and propagates it back to Error detector.
 Error detector generates Error frame request for Protocol control FSM.
 An example of 
\color red
CRC check
\color inherit
 mechanism and detection of 
\color red
CRC error
\color inherit
 is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:crc-check"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
ACK error
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
ACK
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF, Arbitration, Control, Data, Stuff Count, CRC, CRC Delimiter, ACK Delimiter,
 End of Frame, Intermission, Bus idle, Error frame, Overload frame
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
ACK error
\color inherit
 is detected by Protocol control FSM when unit is 
\color red
transmitter
\color inherit
, 
\color red
recessive
\color inherit
 bit is received, and unit is not in Self test mode (frame valid also without
 ACK dominant).
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Error detection rules (part 2)
\begin_inset CommandInset label
LatexCommand label
name "tab:Error-detection-rules-2"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="30.5line%">
<column alignment="left" valignment="top" width="63line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN frame field
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Condition
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If 
\color red
recessive
\color inherit
 bit is received, 
\color red
form error
\color inherit
 is detected.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
r0
\color inherit
 bit after 
\color red
EDL
\color inherit
/
\color red
r1
\color inherit
 bit in frame with 
\color red
extended identifier 
\color inherit
or 
\color red
r0
\color inherit
 bit in CAN FD frames
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If 
\color red
recessive
\color inherit
 bit is received, 
\color red
form error
\color inherit
 is detected when SETTINGS[PEX] = '0'.
 Recessive bit would mean extending beyond CAN FD standard.
 When SETTINGS[PEX] = '1', form error is not detected and CTU CAN FD enters
 integration.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
CRC delimiter
\color inherit
, 
\color red
ACK delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If 
\color red
dominant
\color inherit
 bit is received, 
\color red
form error
\color inherit
 is detected.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
EOF
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If 
\color red
dominant
\color inherit
 bit is detected at all but last bit of EOF, form Error is detected.
 At last bit 
\color red
dominant
\color inherit
 bit means Error frame only for transmitter.
 For receiver, it means Overload condition.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
All but last bit of
\color red
 error delimiter
\color inherit
 and 
\color red
overload delimiter
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If 
\color red
dominant
\color inherit
 bit is received, 
\color red
form error
\color inherit
 is detected.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Form error
\color inherit
 detection
\begin_inset CommandInset label
LatexCommand label
name "tab:Form-error-detection"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="14" columns="2">
<features islongtable="true" longtabularalignment="center">
<column alignment="left" valignment="middle" width="15line%">
<column alignment="left" valignment="top" width="78.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame Field/ Protocol control FSM state 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
SOF
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Dominant
\color inherit
 bit is transmitted.
 
\color red
Bit error
\color inherit
 would be detected when 
\color red
recessive
\color inherit
 value was received.
 Such a situation is treated as 
\color red
form error
\color inherit
, and 
\color red
bit error
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
bus integration
\color inherit
, reintegration
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Recessive
\color inherit
 value is transmitted, receiving 
\color red
dominant
\color inherit
 is not detected as 
\color red
bit error
\color inherit
 since these might represent a frame between other units while CTU CAN FD
 is integrating.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
arbitration field
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Bit error
\color inherit
 is detected by Protocol control FSM, thus 
\color red
bit error
\color inherit
 detected by Bus sampling module is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Control
\color inherit
, 
\color red
data
\color inherit
, 
\color red
stuff count
\color inherit
, 
\color red
CRC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Bit error
\color inherit
 detected by Bus sampling module is ignored if unit is 
\color red
receiver
\color inherit
.
 
\color red
Receiver
\color inherit
 in these fields transmitts only recessive bits and reception of 
\color red
dominant
\color inherit
 bit is not treated as 
\color red
bit error
\color inherit
 since unit is receiving data from other 
\color red
transmitter
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
CRC delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Receiving 
\color red
dominant
\color inherit
 bit during is interpreted as 
\color red
form error
\color inherit
, due to this reason 
\color red
bit error
\color inherit
 detected by Bus sampling module is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
ACK
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Bit error
\color inherit
 is ignored, as is defined in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
ACK delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
During 
\color red
ACK delimiter
\color inherit
, 
\color red
recessive
\color inherit
 value is transmitted and reception of 
\color red
dominant
\color inherit
 value is considered as 
\color red
form error
\color inherit
.
 Due to this reason 
\color red
bit error
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
EOF
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reception of 
\color red
dominant
\color inherit
 bit during 
\color red
EOF
\color inherit
 is treated as 
\color red
form error
\color inherit
 due to this 
\color red
bit error
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Intermission
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Recessive
\color inherit
 value is sent to the bus.
 Receiving 
\color red
dominant
\color inherit
 bit during first or second bit of 
\color red
intermission
\color inherit
 is interpreted as 
\color red
overload frame
\color inherit
.
 Receiving 
\color red
dominant
\color inherit
 bit during third bit of 
\color red
intermission
\color inherit
 is interpreted as 
\color red
SOF
\color inherit
 of next frame.
 Due to these reasons, 
\color red
bit error
\color inherit
 during 
\color red
intermission
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Suspend transmission
\color inherit
, 
\color red
idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Recessive
\color inherit
 value is sent to the bus.
 Receiving 
\color red
dominant
\color inherit
 bit is interpreted as 
\color red
SOF
\color inherit
 of next frame.
 Due to this reason 
\color red
bit error
\color inherit
 during 
\color red
suspend transmission
\color inherit
 and 
\color red
idle
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reintegration wait
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When unit turned 
\color red
bus-off
\color inherit
, it is de-facto off the bus, It shall not transmitt anything unless it
 re-intagrates.
 Due to this reason 
\color red
bit error
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Passive error flag
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Detecting 
\color red
dominant
\color inherit
 bit during 
\color red
passive error flag
\color inherit
 is not interpreted as 
\color red
bit error
\color inherit
 since it is defined like so in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Error delimiter
\color inherit
, 
\color red
Overload delimiter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Recessive
\color inherit
 bit is sent to the bus.
 Receiving 
\color red
dominant
\color inherit
 bit is interpreted as 
\color red
form error
\color inherit
.
 Due to this 
\color red
bit error
\color inherit
 is ignored.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Bit error
\color inherit
 by Bus sampling module exceptions
\begin_inset CommandInset label
LatexCommand label
name "tab:Bit-error-exceptions"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/err_detection_example.pdf
	lyxscale 20
	scale 65

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Error detection example (
\color red
form error
\color inherit
)
\begin_inset CommandInset label
LatexCommand label
name "fig:error-detector"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/CRC_check_sequence.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
CRC check
\color inherit
 and 
\color red
CRC error
\color inherit
 signalling
\begin_inset CommandInset label
LatexCommand label
name "fig:crc-check"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Operation control
\end_layout

\begin_layout Description
File: operation_control.vhd
\end_layout

\begin_layout Standard
Operation control implements Operational state of CTU CAN FD node (
\color red
transmitter
\color inherit
, 
\color red
receiver
\color inherit
, 
\color red
idle
\color inherit
).
 Operation control contains an FSM whose state transition diagram is shown
 in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:fsm-operation-control"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 It is controlled by Protocol control FSM and Fault confinement FSM.
 Rules for control of Operation control FSM are described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:operation-control-state-transitions"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_operation_control.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Operation control FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:fsm-operation-control"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="11" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="71line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Actual state
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Next state
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Off
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When unit is turned on (SETTINGS[ENA]='1'), unit integrates to the bus communica
tion.
 After integration is finished (11 consecutive 
\color red
recessive
\color inherit
 bits received), Protocol control signals 
\series bold
\shape italic
set_idle
\series default
\shape default
.
 Unit becomes 
\color red
idle
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit is 
\color red
idle
\color inherit
 and in 
\color red
sample point
\color inherit
 TX arbitrator signals available frame for transmission, Protocol control
 FSM locks Validated TXT buffer (reffer to 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-arbitrator-buffer-processing"
plural "false"
caps "false"
noprefix "false"

\end_inset

), Protocol control signals 
\series bold
\shape italic
set_transmitter
\series default
\shape default
 and unit becomes 
\color red
transmitter
\color inherit
 of frame from Validated TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Receiver
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit is 
\color red
idle
\color inherit
, there is no available frame for transmission signalled by TX arbitrator.
 
\color red
Dominant
\color inherit
 bit is sampled, Protocol control FSM signals 
\series bold
\shape italic
set_receiver
\series default
\shape default
 and unit becomes 
\color red
receiver
\color inherit
 of next frame.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\end_layout

\end_inset
</cell>
<cell multirow="3" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Receiver
\color inherit
 due to 
\series bold
\shape italic
set_receiver
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit transmitts frame.
 In last bit of 
\color red
intermission
\color inherit
 field, unit is still 
\color red
transmitter
\color inherit
, unit detects 
\color red
dominant
\color inherit
 bit and considers this bit as 
\color red
SOF
\color inherit
 (reffer to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

).
 If there is no available frame for transmission signalled by TX arbitrator,
 Protocol control FSM signals 
\series bold
\shape italic
set_receiver
\series default
\shape default
 and unit becomes 
\color red
receiver
\color inherit
 of following frame.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit is 
\color red
error passive
\color inherit
 and it transmitts a frame.
 It enters 
\color red
suspend transmission
\color inherit
.
 If during 
\color red
suspend transmission
\color inherit
, 
\color red
dominant
\color inherit
 bit is detected, Protocol control FSM issues 
\series bold
\shape italic
set_receiver
\series default
\shape default
 and unit becomes 
\color red
receiver
\color inherit
 of next frame.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Receiver
\color inherit
 due to 
\series bold
\shape italic
arbitration_lost
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If during 
\color red
arbitration
\color inherit
 field 
\color red
recessive
\color inherit
 bit is sent on the bus, but 
\color red
dominant
\color inherit
 bit is monitored by Protocol control FSM, 
\series bold
\shape italic
arbitration_lost
\series default
\shape default
 is signalled and unit becomes 
\color red
receiver
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit transmitts a frame.
 In last bit of 
\color red
intermission
\color inherit
, 
\color red
recessive
\color inherit
 bit is detected (no other unit is attempting to transmitt frame) and there
 is no available frame for transmission signalled by TX arbitrator.
 Protocol control FSM issues 
\series bold
\shape italic
set_idle
\series default
\shape default
 command and unit becomes 
\color red
idle
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Receiver
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit receives a frame.
 In last bit of 
\color red
intermission
\color inherit
, available frame for transmission is signalled by TX arbitrator.
 Protocol control FSM signals 
\series bold
\shape italic
set_transmitter
\series default
\shape default
 and unit becomes 
\color red
transmitter
\color inherit
 of frame from Validated TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Receiver
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Idle
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unit receives a frame.
 In last bit of 
\color red
intermission
\color inherit
, there is no available frame for transmission signalled by TX arbitrator,
 
\color red
recessive
\color inherit
 bit is monitored (no other unit is attempting to transmitt frame), then
 Protocol control FSM issues 
\series bold
\shape italic
set_idle
\series default
\shape default
 command and unit becomes 
\color red
idle
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Idle
\color inherit
, 
\color red
Transmitter
\color inherit
, 
\color red
Receiver
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Off
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Fault confinement FSM signals that unit is 
\color red
bus-off
\color inherit
 or unit is disabled (SETTINGS[ENA] = '0').
 In next 
\color red
sample point
\color inherit
, unit becomes 
\begin_inset Quotes eld
\end_inset

Off
\begin_inset Quotes erd
\end_inset

.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Operation control FSM - state transitions
\begin_inset CommandInset label
LatexCommand label
name "tab:operation-control-state-transitions"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsection
Fault confinement
\end_layout

\begin_layout Description
File: fault_confinement.vhd
\end_layout

\begin_layout Standard
Fault confinement module implements following functionality:
\end_layout

\begin_layout Itemize

\color red
Transmitt error counter 
\color black
(TEC)
\color inherit
/
\color red
 receive
\color inherit
 
\color red
error counters 
\color black
(REC)
\color inherit
 according to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Itemize
Rules for manipulation of TEC and REC.
\end_layout

\begin_layout Itemize

\color red
Fault confinement state
\color inherit
 of node (
\color red
error active
\color inherit
, 
\color red
error passive
\color inherit
, 
\color red
bus-off
\color inherit
).
\end_layout

\begin_layout Itemize
Set of special error counters to distuinguish between errors in 
\color red
nominal bit rate
\color inherit
 and 
\color red
data bit rate
\color inherit
.
\end_layout

\begin_layout Standard
Fault confinement block diagram is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:fault-confinement-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_Fault_confinement.pdf
	lyxscale 20
	scale 90

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Fault confinement block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:fault-confinement-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
TEC and REC counters are controlled by Protocol control FSM via as described
 in 12.1.3.3 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
 Detection of special conditions stated in 12.1.4.2 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

 is implemented in Fault confinement rules module.
 Error counters module implements counters as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:error-counters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Each counter can be modified from Memory registers via CTR_PRES register
 when CTU CAN FD is in Test mode (MODE[TSTM] = '1').
 
\color red
Fault confinement state
\color inherit
 as defined in 12.1.4.1 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

 is implemented by Fault confinement FSM.
 State transition diagram of Fault confinement FSM is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:fsm-fault-confinement"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Threshold for Error warning limit detection (EWL) and transition to 
\color red
error passive
\color inherit
 (ERP) can be configured from Memory registers when device is in Test mode
 (MODE[TSTM] = '1').
 Transition from 
\color red
bus-off
\color inherit
 to 
\color red
error active
\color inherit
 is performed after reintegration (
\series bold
\shape italic
\color black
set_err_active
\series default
\shape default
\color inherit
 is signalled by Protocol control FSM).
 Reffer to 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Reintegration-counter"
plural "false"
caps "false"
noprefix "false"

\end_inset

 for description of Reintegration counter operation.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_fault_confinement.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Fault confinement FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:fsm-fault-confinement"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="71line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Counter Name
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD standard name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Receive error counter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
REC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Incremented, decremented as described in 12.1.4.2 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmitt error counter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TEC
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Incremented, decremented as described in 12.1.4.2 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Nominal error counter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Incremented by 1 for each error detected during 
\color red
nominal bit rate
\color inherit
.
 No influence on 
\color red
fault confinement state
\color inherit
 of CTU CAN FD.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data error counter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Incremented by 1 for each error detected during 
\color red
data bit rate
\color inherit
.
 No influence on 
\color red
fault confinement state
\color inherit
 of CTU CAN FD.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Error counters
\begin_inset CommandInset label
LatexCommand label
name "tab:error-counters"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Description
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsection
Bit stuffing
\end_layout

\begin_layout Description
File: bit_stuffing.vhd
\end_layout

\begin_layout Standard
Bit stuffing module implements following functionality:
\end_layout

\begin_layout Itemize
Inserts 
\color red
stuff bits
\color inherit
 to data transmitted by Protocol control (regular and 
\color red
fixed stuff bits
\color inherit
).
\end_layout

\begin_layout Itemize
Halts CAN core for one bit time when 
\color red
stuff bit
\color inherit
 is inserted.
\end_layout

\begin_layout Itemize
Counts number of 
\color red
stuff bits
\color inherit
 modulo 8 for transmission of 
\color red
stuff count
\color inherit
 field.
\end_layout

\begin_layout Itemize
Inserts 
\color red
stuff bit
\color inherit
 in the beginning of 
\color red
stuff count field
\color inherit
 or 
\color red
CRC field
\color inherit
 of CAN FD Frame.
\end_layout

\begin_layout Standard
Bit stuffing module processes data transmitted by Protocol control in Stuff
 pipeline stage.
 Bit stuffing module operates in two modes as described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-stuffing-modes"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When Bit stuffing is enabled, it inserts bit of opposite polarity to transmitte
d bit stream based on Bit stuffing mode.
 Data are processed by Bit stuffing module with one clock cycle delay (output
 is registered).
 When Bit stuffing module is disabled, it propagates data from input to
 output without inserting 
\color red
stuff bits
\color inherit
 , but still with one clock cycle delay.
 Input data are processed in Stuff pipeline stage regardless of the fact
 if Bit stuffing module is enabled or disabled (Input is not combinatorially
 bypassed when Bit stuffing module is disabled).
 Bit stuffing module is enabled only when unit is 
\color red
transmitter
\color inherit
 of CAN Frame.
 When unit is 
\color red
receiver
\color inherit
, Bit stuffing module is disabled and only propagates recessive bit values
 from input to output.
 Bit stuffing module counts number of inserted 
\color red
stuff bits
\color inherit
 in Regular Bit stuffing mode in counter of 
\color red
stuff bits 
\color inherit
(this counter is then used in 
\color red
stuff count
\color inherit
 frame field).
 A basic sequence of Bit stuffing module operation is described in Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-stuffing-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
When bus is 
\color red
idle
\color inherit
 and transmission of frame starts, 
\color red
SOF
\color inherit
 bit is the first bit which is processed by Bit stuffing module.
 If unit samples 
\color red
dominant
\color inherit
 bit during third bit of 
\color red
intermission
\color inherit
, 
\color red
bus idle
\color inherit
 or 
\color red
suspend
\color inherit
 
\color red
transmission
\color inherit
, this bit is considered as 
\color red
SOF
\color inherit
 bit (see 10.4.2.2 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

).
 Such bit is counted as first 
\color red
dominant
\color inherit
 bit by Bit stuffing module.
 Bit stuffing module is disabled when unit reaches 
\color red
CRC delimiter
\color inherit
 frame field.
 Bit stuffing module is not disabled in last bit of 
\color red
CRC sequence
\color inherit
 so that 
\color red
stuff bit
\color inherit
 can be inserted behind the last bit of 
\color red
CRC sequence
\color inherit
.
 When CTU CAN FD loses arbitration (turns 
\color red
receiver
\color inherit
), Bit stuffing module is disabled.
 An example of Bit stuffing module operation during whole frame is shown
 in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:bit-stuffing-detailed-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 If an 
\color red
error
\color inherit
 is detected (
\color red
error frame
\color inherit
 is requested by Error detector), Bit stuffing module is disabled.
 Bit stuffing module is enabled only during fields which shall be coded
 by 
\color red
bit stuffing
\color inherit
 as described in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="top" width="71line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit stuffing mode
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff rule length
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Regular
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When 5 consecutive bits of equal value are processed, bit of opposite value
 is inserted.
 Inserted 
\color red
stuff bit
\color inherit
 counts as first bit of next sequence of 5 equal consecutive bits (
\color red
bit stuffing
\color inherit
 is recursive).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Fixed
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When 4 bits are processed (regardless of their value), a bit of opposite
 value than last bit of these 4 bits is inserted on output of Bit stuffing
 module.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit stuffing modes
\begin_inset CommandInset label
LatexCommand label
name "tab:bit-stuffing-modes"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="10" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit stuffing module is disabled, there is no transmission / reception in
 progress by CTU CAN FD.
 Counter of equal consecutive bits is 1.
 Bit stuffing module only propagates 
\color red
recessive
\color inherit
 value to output in Stuff pipeline stage.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmission starts (unit becomes 
\color red
transmitter
\color inherit
), Bit stuffing module is enabled.
 Length of Stuff rule is configured to 5 by Protocol control FSM.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit stuffing module processes bits from Protocol control in Stuff pipeline
 stage.
 Counter of equal consecutive bits is incremented by 1 for each processed
 bit of equal polarity (with respect to previous bit).
 When bit of opposite polarity is processed, counter of equal consecutive
 bits is set to 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Counter of equal consecutive bits reaches length of Stuff rule.
 Instead of propagating processed bit to output, Bit stuffing inserts bit
 of opposite polarity on output.
 Bit stuffing module halts to Protocol control.
 Protocol control remains halted for one bit.
 Counter of 
\color red
stuff bits
\color inherit
 is incremented by 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
After one 
\color red
bit time
\color inherit
 for which Protocol control was halted, it continues in transmission.
 Bit stuffing module continues in processing data transmitted by Protocol
 control.
 Counter of equal consecutive bits is incremented after insertion of 
\color red
stuff bit
\color inherit
 to account for recursive behaviour of 
\color red
bit stuffing
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multicolumn="1" alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\emph on
Applies only for CAN FD frames
\emph default

\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{cyan}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD Frame advances to last bit of frame field preceding 
\color red
stuff count
\color inherit
 frame field.
 Bit stuffing mode is changed to Fixed.
 Length of Bit stuffing rule is configured to 4.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Stuff bit
\color inherit
 is inserted by Bit stuffing module in the first bit which is processed
 in Fixed Bit stuffing mode (First bit of 
\color red
stuff count
\color inherit
 frame field).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Counter of equal consecutive bits is incremented with each processed bit
 regardless of previous processed bit value.
 
\color red
Stuff bit
\color inherit
 is inserted after each 4 processed bits.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit stuffing module operation
\begin_inset CommandInset label
LatexCommand label
name "tab:bit-stuffing-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/CHART_bit_stuffing.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit stuffing detailed operation
\begin_inset CommandInset label
LatexCommand label
name "fig:bit-stuffing-detailed-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Bit destuffing
\begin_inset CommandInset label
LatexCommand label
name "subsec:Bit-Destuffing"

\end_inset


\end_layout

\begin_layout Description
File: bit_destuffing.vhd
\end_layout

\begin_layout Standard
Bit destuffing module implements following functionality:
\end_layout

\begin_layout Itemize
Discards 
\color red
stuff bits
\color inherit
 from received data on CAN bus (
\color red
regular
\color inherit
 and 
\color red
fixed stuff bits
\color inherit
).
\end_layout

\begin_layout Itemize
Halts CAN core for one bit time when 
\color red
stuff bit
\color inherit
 is discarded.
\end_layout

\begin_layout Itemize
Counts number of 
\color red
de-stuffed bits
\color inherit
 modulo 8 for comparison with 
\color red
received stuff count
\color inherit
 frame field.
\end_layout

\begin_layout Itemize
Discards first 
\color red
fixed stuff bit
\color inherit
 of CAN FD Frame.
\end_layout

\begin_layout Itemize
Detects 
\color red
stuff error
\color inherit
.
\end_layout

\begin_layout Standard
Bit destuffing module processes received data on CAN bus as provided by
 multiplexor in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:CAN-Core-Block-diagam-1"
plural "false"
caps "false"
noprefix "false"

\end_inset

 in Destuff pipeline stage.
 Bit destuffing module operates in two modes as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-destuffing-modes"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Bit destuffing module discards 
\color red
stuff bits
\color inherit
 according to current Bit destuffing mode.
 Discarded 
\color red
stuff bit
\color inherit
 is signalled to Protocol control and it is ignored by Protocol control
 (not shifted to RX shift register, does not affect Protocol control FSM).
 Input data are processed with one clock cycle delay (output is registered).
 When Bit destuffing module is disabled, it only propagates input data to
 output in Destuff pipeline stage without discarding any bit or detecting
 
\color red
stuff error
\color inherit
.
 Bit destuffing module is enabled when unit is 
\color red
transmitter
\color inherit
 or 
\color red
receiver
\color inherit
 since 
\color red
transmitter
\color inherit
 also receives bits transmitted by itself.
 Bit destuffing module contains counter of discarded 
\color red
stuff bits
\color inherit
 in Regular mode.
 This counter is compared with received 
\color red
stuff count field
\color inherit
 as part of CRC check in CAN FD frames.
 A basic sequence of operation is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-destuffing-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
When bus is 
\color red
idle
\color inherit
, unit is in 
\color red
suspend transmission
\color inherit
 or third bit of 
\color red
intermission
\color inherit
, Bit destuffing module processes 
\color red
dominant
\color inherit
 bit (which is subsequently evaluated as 
\color red
SOF
\color inherit
 by Protocol control FSM), then Bit destuffing module considers this bit
 as first bit in sequence of equal consecutive bits.
 Bit destuffing module is disabled when unit reaches 
\color red
CRC delimiter
\color inherit
 frame field.
 Bit destuffing module is not disabled in last bit of 
\color red
CRC sequence
\color inherit
 so that 
\color red
stuff bit
\color inherit
 can be discarded behind the last bit of 
\color red
CRC sequence
\color inherit
.
 When transmission of 
\color red
error frame
\color inherit
 is requested, Bit destuffing module is disabled.
 Bit destuffing module is enabled only during fields which shall be coded
 by 
\color red
bit stuffing
\color inherit
 as described in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="top" width="71line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit destuffing Mode
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuff rule length
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Regular
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When 5 consecutive bits of equal polarity are processed, next bit is discarded.
 If value of discarded bit is equal to previous bit, 
\color red
stuff error
\color inherit
 is detected.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Fixed
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When 4 bits are processed next bit is discarded, next bit is discarded regardles
s of values of previous processed bits.
 If value of discarded bit is equal to previous bit, 
\color red
stuff error
\color inherit
 is detected.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit destuffing modes
\begin_inset CommandInset label
LatexCommand label
name "tab:bit-destuffing-modes"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="10" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit destuffing module is disabled, there is no transmission / reception
 in progress by CTU CAN FD.
 Counter of equal consecutive bits is 1.
 Bit destuffing module only propagates 
\color red
recessive
\color inherit
 value to output in Destuff pipeline stage.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmission or reception of frame starts (unit becomes 
\color red
receiver
\color inherit
), Bit destuffing module is enabled.
 Destuff rule length is configured to 5 by Protocol control FSM.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit destuffing module processes bits in Destuff pipeline stage.
 Counter of equal consecutive bits is incremented by 1 for each processed
 bit of equal polarity (with respect to previous bit).
 When bit of opposite polarity is processed, Counter of equal consecutive
 bits is set to 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Counter of equal consecutive bits reaches length of Stuff rule.
 Following bit is discarded (not processed) and signalled to Protocol control
 FSM as 
\begin_inset Quotes eld
\end_inset

Destuffed
\begin_inset Quotes erd
\end_inset

.
 Protocol control ignores such a bit and its processing of received data
 remains halted for one 
\color red
bit time
\color inherit
.
 Number of discarded 
\color red
stuff bits
\color inherit
 (counter of discarded 
\color red
stuff bits
\color inherit
) is incremented by 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
After one 
\color red
bit time
\color inherit
 for which Protocol control was halted, Bit stuffing module processes next
 bit.
 This bit is also processed by Protocol control.
 Counter of equal consecutive bits is incremented after discarding 
\color red
stuff bit
\color inherit
 to account for 
\begin_inset Quotes eld
\end_inset

recursive
\begin_inset Quotes erd
\end_inset

 behaviour of 
\color red
bit destuffing
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multicolumn="1" alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\emph on
Applies only for CAN FD frames
\emph default

\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{cyan}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD Frame advances to the end of frame field preceding 
\color red
stuff count
\color inherit
 frame field.
 Bit destuffing mode is changed to Fixed.
 Destuff rule length is configured to 4.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Stuff bit
\color inherit
 is discarded by Bit destuffing module in the first bit which is processed
 in Fixed Bit Stuffing mode (first bit of 
\color red
stuff count
\color inherit
 frame field).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Counter of equal consecutive bits is incremented with each processed bit
 regardless of previous processed bit value.
 
\color red
Stuff bit
\color inherit
 is discarded after each 4 processed bits.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit destuffing module operation
\begin_inset CommandInset label
LatexCommand label
name "tab:bit-destuffing-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsection
CAN CRC
\end_layout

\begin_layout Description
File: can_crc.vhd
\end_layout

\begin_layout Standard
CAN CRC implements following functionality:
\end_layout

\begin_layout Itemize
Calculates 
\color red
CRC sequences
\color inherit
 according to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

 (for ISO CAN FD) and according to 
\begin_inset CommandInset citation
LatexCommand cite
key "key-6"
literal "false"

\end_inset

 (for non-ISO CAN FD).
\end_layout

\begin_layout Itemize
Chooses appropriate input and trigger for calculation of CRC sequence.
\end_layout

\begin_layout Standard
Block diagram of CAN CRC is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:can-crc-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_CAN_CRC.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
CAN CRC block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:can-crc-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
CAN CRC contains 3 CRC calculation modules (
\color red
CRC_15
\color inherit
, 
\color red
CRC_17
\color inherit
, 
\color red
CRC_21
\color inherit
).
 
\color red
CRC_15
\color inherit
 is calculated from data without 
\color red
stuff bits
\color inherit
.
 
\color red
CRC_17
\color inherit
 and 
\color red
CRC_21
\color inherit
 are calculated from data with 
\color red
stuff bits
\color inherit
 inserted.
 CRC register is preloaded to 
\color red
CRC_INIT_VECTOR
\color inherit
 upon enabling of CRC calculation (before first bit is processed).
 When a CRC calculation module is enabled, next step of CRC calculation
 is executed every bit of CAN frame.
 A pseudo-code for CRC calculation is shown in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
Data input to CRC calculation is different based on part of the CAN frame
 where CRC calculation is executed and operational state of CTU CAN FD.
 During 
\color red
arbitration field
\color inherit
, or when speculative enable is used (during 
\color red
bus idle
\color inherit
, 
\color red
intermission
\color inherit
 or 
\color red
suspend transmission
\color inherit
), CRC is calculated from received data as there can be multiple units transmitt
ing on the bus at once, and correct value (when bus has settled in 
\color red
sample point
\color inherit
) must be used for calculation.
 After 
\color red
arbitration field
\color inherit
 , 
\color red
transmitter
\color inherit
 calculates CRC from transmitted data, and 
\color red
receivers
\color inherit
 calculate CRC from received data.
 Calculation step from transmitted data is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:crc-calculation-transmitter"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and from received data is shown in 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:crc-calculation-receiver"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
After 
\color red
arbitration field
\color inherit
, source of data for CRC calculation changes from transmitted to received
 data.
 Pipeline stage when next step of CRC calculation is executed differs based
 on source of input data (if received data are used, input data are not
 valid before 
\color red
sample point
\color inherit
) as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:can-crc-calculation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When 
\color red
CRC_17
\color inherit
/
\color red
CRC_21
\color inherit
 execute CRC calculation step from 
\color red
stuffed
\color inherit
/
\color red
destuffed
\color inherit
 bit, 
\color red
CRC_15
\color inherit
 remains unchagned (according trigger signal is gated).
 CRC calculation step can be enabled by means of two enable signals: Regular
 enable and Speculative enable.
 Meaning of these two signals is explained in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:can-crc-enable-signals"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/crc_transmitter.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
CRC calculation - TX Data stream
\begin_inset CommandInset label
LatexCommand label
name "fig:crc-calculation-transmitter"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/crc_receiver.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
CRC calculation - RX Data stream
\begin_inset CommandInset label
LatexCommand label
name "fig:crc-calculation-receiver"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="8.8line%">
<column alignment="left" valignment="top" width="8line%">
<column alignment="left" valignment="top" width="42line%">
<column alignment="left" valignment="top" width="30line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC module
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data stream
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data input for CRC calculation
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pipeline stage when calculation step is executed
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC_15
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmitted data on output of Protocol control.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Received data on input of Protocol control.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC_17
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmitted data on output of Bit stuffing module.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff + 1 clock cycle
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Received data on input of Bit destuffing module.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC_21
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmitted data on output of Bit stuffing module.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff + 1 clock cycle
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Received data on input of Bit destuffing module.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
CAN CRC calculation
\begin_inset CommandInset label
LatexCommand label
name "tab:can-crc-calculation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="78.6line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN CRC Enable signal
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Regular enable
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When CRC module is enabled by regular enable signal, it executes next step
 of calculation in according pipeline stage regardless of input data value
 to be processed.
 This enable signal is used during CAN frame fields from 
\color red
SOF
\color inherit
 until end of 
\color red
data field
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Speculative enable
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When CRC module is enabled by speculative enable signal, it executes next
 step of calculation in according pipeline stage only when input data value
 to be processed is 
\color red
dominant
\color inherit
 (logic 0) and recessive value is ignored.
 Speculative enable is used in 
\color red
suspend transmission
\color inherit
, last bit of 
\color red
intermission
\color inherit
 and 
\color red
bus idle
\color inherit
 when 
\color red
dominant
\color inherit
 value is sampled and this value is interpreted as 
\color red
SOF
\color inherit
 by Protocol control (as this bit needs to be already taken into account
 for CRC calculation).
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
CAN CRC enable signals
\begin_inset CommandInset label
LatexCommand label
name "tab:can-crc-enable-signals"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Trigger multiplexor
\end_layout

\begin_layout Description
File: trigger_mux.vhd
\end_layout

\begin_layout Standard
Trigger multiplexor creates trigger signals for other blocks within CAN
 core from trigger signals generated by Prescaler as described in Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:trigger-signals"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Trigger-generator"
plural "false"
caps "false"
noprefix "false"

\end_inset

 on how are trigger signals generated by Prescaler.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="middle" width="10line%">
<column alignment="left" valignment="top" width="71line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Trigger Name
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pipeline stage
\end_layout

\begin_layout Plain Layout
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control TX Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to shift TX shift register in Protocol control.
 Gated when there is 
\color red
stuff bit
\color inherit
 inserted, this corresponds to halting Protocol control for 1 bit time as
 described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-stuffing-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control RX Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to shift RX shift register in Protocol control, update of Protocol
 control FSM state, manipulation of Control counter and Retransmitt Counter.
 Gated when 
\color red
stuff bit
\color inherit
 is discarded, this corresponds to halting Protocol control for 1 bit time
 as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-destuffing-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit Stuffing Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to process transmitted data by Bit stuffing module.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit Destuffing Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destuff
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to process received data by Bit destuffing module.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC TX WBS Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff + 1 clock cycle
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to enable CRC calculation step for 
\color red
CRC_17
\color inherit
 / 
\color red
CRC_21
\color inherit
 when CRC calculation step is executed from transmitted data.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC TX NBS Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Stuff
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to enable CRC calculation step for 
\color red
CRC_15
\color inherit
 when CRC calculation step is executed from transmitted data.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC RX WBS Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to enable CRC calculation step for 
\color red
CRC_17
\color inherit
 / 
\color red
CRC_21
\color inherit
 when CRC calculation step is executed from received data.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC RX NBS Trigger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Process
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used to enable CRC calculation step for 
\color red
CRC_15
\color inherit
 when CRC calculation step is executed from received data.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Trigger signals 
\begin_inset CommandInset label
LatexCommand label
name "tab:trigger-signals"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Bus traffic counters 
\begin_inset CommandInset label
LatexCommand label
name "subsec:Bus-traffic-counters"

\end_inset


\end_layout

\begin_layout Description
File: bus_traffic_counters.vhd
\end_layout

\begin_layout Standard
Bus traffic counters contains two 32-bit counters (TX frame counter and
 RX frame counter).
 TX frame counter counts succesfully transmitted frames (without 
\color red
error frame
\color inherit
 or 
\color red
arbitration lost
\color inherit
) and is incremented by 1 for each such transmitted frame.
 RX frame counter counts succesfully received frames (without 
\color red
error frame
\color inherit
) and is incremented by 1 for each such a frame.
 If unit is 
\color red
transmitter
\color inherit
 in Loopback mode (it also receives frame transmitted by itself), both counters
 are incremented upon succesfull transmission/reception.
 In such case, TX frame counter is incremented when transmitted frame is
 considered valid and RX frame counter is incremented when received is considere
d valid as defined in 10.7 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

).
 
\end_layout

\begin_layout Standard
Both counters can be erased by SW via COMMAND[TXFRCRST] and COMMAND[RXFRCRST]
 register.
 Value of traffic counters can be read out from TX_FR_CTR and RX_FR_CTR
 registers.
 Bus traffic counters are instantiated only when 
\series bold
\shape italic
sup_traffic_counters
\series default
\shape default
=
\series bold
\shape italic
true
\series default
\shape default
.
 When Bus traffic counters are not instantiated, access to TX_COUNTER and
 RX_COUNTER registers are reserved and writes to COMMAND[TXFRCRST] and COMMAND[R
XFRCRST] have no effect.
\end_layout

\begin_layout Section
RX buffer
\begin_inset CommandInset label
LatexCommand label
name "sec:RX-Buffer"

\end_inset


\end_layout

\begin_layout Description
File: rx_buffer.vhd
\end_layout

\begin_layout Standard
RX buffer implements following functionality:
\end_layout

\begin_layout Itemize
Stores CAN frames and Errorframes to FIFO memory as CAN frame progresses.
\end_layout

\begin_layout Itemize
Counts number of stored frames in FIFO.
\end_layout

\begin_layout Itemize
Provides read interface for Memory registers.
\end_layout

\begin_layout Itemize
Aborts storing of CAN frame in case of an 
\color red
error frame
\color inherit
 request or overrun.
\end_layout

\begin_layout Standard
Block diagram of RX buffer is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-buffer-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_RX_Buffer.pdf
	lyxscale 20
	scale 60

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
RX buffer contains FIFO memory (details of actual RAM memory are described
 in 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Memories"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 The FIFO memory stores received CAN FD frames, or Error frames (if CTU
 CAN FD is configured to do so).
 Size of RX buffer memory is configurable by 
\series bold
\shape italic
rx_buffer_size
\series default
\shape default
.
 Lower limit on size of RX buffer RAM is set to be able to store at least
 1 CAN FD frame with 64 byte data payload.
 Format of CAN FD frame within the memory is described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:CAN-frame-format"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and visualized in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-buffer-memory-format"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Size of CAN frame within RX buffer memory spans from 4 to 20 32-bit memory
 words.
 
\color red
Remote frames
\color inherit
, frames with no 
\color red
data field
\color inherit
 and Error frames span 4 memory words (Metadata, Identifier, Timestamp upper
 and Timestamp lower).
 Each 4 bytes of 
\color red
data field
\color inherit
 span one memory word.
 Longest frame with 64 data bytes spans 20 memory words (Metadata, Identifier,
 Timestamp upper, Timestamp lower and 16 data words).
\end_layout

\begin_layout Standard
RX frame is stored to FIFO by Storing protocol described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Storing-protocol"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 RX Frame is read from FIFO by Reading protocol described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Reading-protocol"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 RX buffer contains pointers to FIFO which are described in detail in Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-buffer-pointers"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 RX buffer can by flushed by issuing Release receive buffer command (writing
 logic 1 to COMMAND[RRB]).
 In such case, all pointers are reset to zero as well as counter of stored
 frames (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Reading-protocol"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 If Release receive buffer command is issued by SW during storing of CAN
 frame, overrun flag is set, and upon the end of actual frame this frame
 is discarded, and Raw write pointer is reset to value of previous Comited
 write pointer.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="33.5line%">
<column alignment="left" valignment="top" width="15line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pointer
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Incremented by 1
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pre-loaded
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Pre-load value
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Raw write pointer
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When a word is written to RX buffer RAM (Metadata, Identifier, Timestamp
 or Data word)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When Reception abort command is issued or, Reception valid command is issued
 and Overflow occured before in the frame.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Commited write pointer
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Commited write pointer
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When frame is commited.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Raw write pointer
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamp write pointer
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
During storing of Timestamp lower word.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When Raw write pointer points to Lower timestamp word of frame which is
 actually being stored.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Raw write pointer
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read pointer
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When a word is read from RX buffer.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer pointers
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-buffer-pointers"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/RX_Buffer_layout.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer memory format
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-memory-format"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Storing protocol
\begin_inset CommandInset label
LatexCommand label
name "subsec:Storing-protocol"

\end_inset


\end_layout

\begin_layout Standard
Protocol control FSM forms 
\begin_inset Quotes eld
\end_inset

Master
\begin_inset Quotes erd
\end_inset

 side of Storing protocol, and issues commands as described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-buffer-commands"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Commands from Protocol control FSM are filtered by Frame filters before
 being connected to RX buffer.
 Commands pass CAN fame filters when RX frame matches CAN frame filters
 as described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Frame-Filters"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 If received frame does not match CAN frame filters, commands are gated,
 and does not reach RX buffer within current CAN frame.
 RX buffer FSM forms 
\begin_inset Quotes eld
\end_inset

Slave
\begin_inset Quotes erd
\end_inset

 side of this protocol, it receives commands and reacts upon them.
 State transition diagram of RX buffer FSM is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-buffer-fsm"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Commands are issued by Protocol control FSM continously as reception of
 CAN frame progresses.
 Commands are issued by Protocol control FSM only when unit is 
\color red
receiver
\color inherit
 of a frame, or when Loopback mode (SETTINGS[ILBP] = '1') is enabled.
 An example of Storing protocol is shown in Figures 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Storing-protocol"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-buffer-storing-error"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Storing protocol is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-buffer-storing-detailed"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 If CTU CAN FD is configured to log Error frames to RX buffer, then upon
 Error Frame (Receive Abort Command), RX buffer stores 4 words that represents
 the Error frame.
\end_layout

\begin_layout Standard
As CAN frame is being stored, the frame can't be read out by SW via Memory
 registers.
 Only after the frame is succesfully received without 
\color red
error frame
\color inherit
 or overrun (last bit of 
\color red
EOF
\color inherit
 field), it becomes available for readout by SW (the frame is so called
 
\begin_inset Quotes eld
\end_inset

commited
\begin_inset Quotes erd
\end_inset

).
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/rx_buffer_storing_protocol.pdf
	lyxscale 20
	scale 50

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer storing protocol - succesfull reception
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-storing-ok"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/rx_buffer_storing_protocol_error.pdf
	lyxscale 20
	scale 50

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer storing protocol - Error frame
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-storing-error"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_RX_Buffer.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-fsm"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="25line%">
<column alignment="left" valignment="top" width="25line%">
<column alignment="left" valignment="top" width="28.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Command
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Issued in CAN frame part
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action performed
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Source of stored information to RX buffer RAM
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Store metadata
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
At the end of 
\color red
data length code
\color inherit
 field.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Store Metadata word, Identifier word and zeroes to Timestamp words.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame metadata and 
\color red
identifier
\color inherit
 from capture registers in RX shift register in Protocol control.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Store data
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
After multiple of 4 bytes of 
\color red
data field
\color inherit
 elapsed and at the end of 
\color red
data field
\color inherit
.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Store Data word (4 bytes).
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX shift register in Protocol control.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reception valid
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
In 
\color red
sample point
\color inherit
 of last bit of 
\color red
EOF
\color inherit
 field.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamp is stored and afterwards CAN Frame is commited to memory.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamp capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reception abort
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When 
\color red
error frame
\color inherit
 is transmitted.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame storing is aborted, Raw write pointer is reverted to last Commited
 write pointer.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer commands
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-buffer-commands"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="10" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Reception of CAN frame starts.
 If received frame timestamp is configured to be captured at 
\color red
SOF
\color inherit
 (RX_SETTINGS[RTSOPT]), the timestamp is stored to a Timestamp capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Identifier is received to RX shift register in Protocol control, and stored
 to a dedicated capture register.
 Metadata are stored to dedicated capture registers in Protocol control.
 See 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:RX-Shift-Register"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
At the end of 
\color red
control field
\color inherit
, it is already clear whether unit is 
\color red
transmitter
\color inherit
 or 
\color red
receiver
\color inherit
.
 It can no longer happend that a word will be stored to RX buffer and unit
 will turn 
\color red
receiver
\color inherit
 due to losing arbitration.
 if CTU CAN FD is 
\color red
receiver
\color inherit
 or in Looback mode, Protocol control FSM issues Store metadata command.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX buffer FSM stores Frame format word, received CAN 
\color red
identifier
\color inherit
 to Identifier word and zeroes to Timestamp words.
 This happends during 4 consecutive clock cycles after 
\begin_inset Quotes eld
\end_inset

Store Metadata
\begin_inset Quotes erd
\end_inset

 command.
 Raw write pointer is incremented by 1 during each of these cycles.
 When Raw write pointer points to Lower Timestamp word, its value is captured
 to Timestamp write pointer.
 After this step Raw write pointer points to first Data word.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data field
\color inherit
 of CAN frame starts.
 After each 4 bytes are received on the CAN bus, Protocol control FSM issues
 Store data command.
 The 4 bytes are stored to a single word in RX buffer RAM, and Raw write
 pointer is incremented by 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
At the end of last bit of 
\color red
data field
\color inherit
, Protocol control FSM issues Store data command if the length of data field
 is not multiple of bytes.
 Remaining bytes are stored to RX buffer RAM, and Raw write pointer is increment
ed.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN frame progresses to 
\color red
EOF
\color inherit
 field.
 In 
\color red
sample point
\color inherit
 of 
\color red
EOF
\color inherit
 field, received frame is considered valid (if no 
\color red
error frame
\color inherit
 occurred).
 Protocol control FSM issues 
\begin_inset Quotes eld
\end_inset

Reception valid
\begin_inset Quotes erd
\end_inset

 command.
 If received frame timestamp shall be taken in EOF, it is captured to a
 capture register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Timestamp is stored from its capture register (by means of Timestamp write
 pointer), to Timestamp low and Timestamp high memory words of RX buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If overrun condition did not occur during storing of current frame, frame
 is commited to memory, Raw write pointer moves to Commited write pointer
 and number of frames in RX buffer (Frame counter) is incremented.
 If overrun condition or Release receiver buffer command did occur during
 storing of current frame, frame is not commited to memory, Raw Write Pointer
 is reverted to Commited Write Pointer and number of frames in RX buffer
 remains unchanged.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer storing protocol - detailed description
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-buffer-storing-detailed"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Overrun flags
\end_layout

\begin_layout Standard
RX buffer maintains two overrun flags: User overrun flag and Internal overrun
 flag.
 Both overrun flags are set when RX buffer FSM intents to store a word to
 RX buffer RAM, and RX buffer RAM is full (Overrun condition).
 Internal overrun flag is reset at the end of CAN frame.
 User overrun flag is reset by SW writing COMAND[CDO]=1.
 When the frame is error-free (no 
\color red
error frame
\color inherit
), but overrun condition occured at some point before in the frame (Internal
 overrun flag is set), frame is discarded (not commited) and Write pointers
 are reverted to their previous commited value.
\end_layout

\begin_layout Subsection
Received frame timestamp
\end_layout

\begin_layout Standard
RX buffer implements Timestamping of received frames.
 Such timestamp is created by sampling 
\series bold
\shape italic
timestamp
\series default
\shape default
 input of CTU CAN FD in 
\color red
sample point
\color inherit
 of 
\color red
SOF
\color inherit
 or 
\color red
EOF
\color inherit
 bits (configured by RX_SETTINGS[RTSOP]).
 In 
\color red
sample point
\color inherit
 of these bits, 
\series bold
\shape italic
timestamp
\series default
\shape default
 is captured to capture register.
 Timestamp is stored to RX bufer RAM from capture register at the end of
 CAN frame.
 As position of Timestamp memory words within RX buffer RAM is lower than
 Data words, when timestamp is about to be stored (in 
\color red
sample point
\color inherit
 of 
\color red
EOF
\color inherit
), Raw write pointer is pointing one memory word behind last word of CAN
 frame.
 Due to this reason, Raw write pointer can't be used to store received frame
 timestamp, and dedicated Timestamp write pointer is used.
 This pointer is loaded by RX buffer FSM to point to first Timestamp word
 in RX buffer RAM.
\end_layout

\begin_layout Subsection
RX buffer Parity
\end_layout

\begin_layout Standard
If enabled at synthesis time by 
\series bold
\shape italic
sup_parity
\series default
\shape default
 , each RX buffer memory word has additional parity bit.
 The parity bit is stored as the word is being stored to the RX buffer RAM.
 When the RX buffer word is being read, the parity is computed again and
 compared with stored parity.
 If the computed and stored parity are not equal, a flag is set in Memory
 registers.
 
\end_layout

\begin_layout Subsection
Reading protocol
\begin_inset CommandInset label
LatexCommand label
name "subsec:Reading-protocol"

\end_inset


\end_layout

\begin_layout Standard
CAN frame in RX buffer is read by SW.
 To read the frame SW executes read accesses to RX_DATA register.
 There are two modes (distuiguished by MODE[RXBAM] bit) in which RX buffer
 can be read:
\end_layout

\begin_layout Itemize
Automated mode (default) - SW must read via 32 bit accesses.
 When RX_DATA register is read, RX buffer read pointer automatically moves
 to next word.
\end_layout

\begin_layout Itemize
Manual mode - SW can read via 8/16/32 bit accesses.
 When RX_DATA register is read, RX buffer read pointer is NOT moved automaticall
y to next word.
 To move RX buffer to next word, use must issue COMMAND[RXRPMV]).
 This mode can be used in systems which are incapable of executing 
\begin_inset Quotes eld
\end_inset

atomic
\begin_inset Quotes erd
\end_inset

 32 bit accesses, and require reading by 8 or 16 bit accesses.
\end_layout

\begin_layout Standard
Behavior of RX buffer during reads is described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:rx-buffer-read-protocol"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Read pointer is incremented after each word is read, either manually or
 automatically (an exception to this rule is when FIFO is empty).
 RX buffer supports single reads (Read indication asserted for one clock
 cycle) and also continous burst read (Read indication asserted for several
 consecutive clock cycles).
 Since RX buffer RAM has one clock cycle delay on data output, RAM read
 address is speculatively multiplexed between Read pointer and Read pointer
 + 1 as shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:rx-buffer-speculation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Due to this speculation RX buffer read pre-feteches data from next memory
 word instead of memory word given by Read pointer.
 This speculation is executed to support burst read.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read pointer points to Frame Format word of most recently stored frame in
 RX buffer.
 Output of RX buffer RAM contain Frame Format word.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW reads from RX_DATA register (Frame Format word).
 Auxiliarly counter is loaded to value of RWCNT.
 Read pointer is incremented by 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW now knows value of RWCNT (number of remaining words in currently read
 frame).
 SW reads from RX_DATA register RWCNT times.
 Read Pointer is incremented by 1 and auxiliarly counter is decremented
 by 1 after each of these reads.
 
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
During last read (when auxiliarly counter transits from 1 to 0), Frame counter
 is decremented by 1.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer - read protocol
\begin_inset CommandInset label
LatexCommand label
name "tab:rx-buffer-read-protocol"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/rx_buffer_pointer_speculation.pdf
	lyxscale 20
	scale 60

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
RX buffer - Read pointer speculation
\begin_inset CommandInset label
LatexCommand label
name "fig:rx-buffer-speculation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
RX buffer contains Frame counter (readable by SW via RX_STATUS[RXFRC]).
 Frame counter holds amount of CAN frames actually stored in RX buffer.
 Frame counter is incremented by 1 when a frame is commited to RX buffer.
 Since RX buffer RAM is read word by word, RX buffer counts each read word
 from Memory registers and decrements Frame counter only when whole frame
 was read.
 If new frame is committed at the same time as last word of another frame
 is read, Frame counter remains unchanged.
 Manipulation with Frame counter is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:frame-counter-handling"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame counter is 0.
 CAN frame is being received and stored to RX buffer RAM.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame ends and it is commited to RX buffer, Frame Counter is incremented
 to 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read Pointer points to the first word of CAN frame (Frame format word).
 Memory registers issue a read from RX buffer.
 RX buffer RAM output contains Frame Format word.
 RX buffer loads value of RWCNT (Read word count) to an auxiliarly counter.
 Frame counter remains 1 and Read Pointer increments and points to Identifier
 word.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory registers issue RWCNT - 1 number of reads from RX buffer and Read
 pointer increments by 1 on each read.
 Auxiliarly register decrements by 1 each read.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory registers issue a read from RX buffer (reading last word of CAN frame).
 Auxiliarly register indicates that last word of frame is read and Frame
 counter is decremented by 1.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Frame counter handling
\begin_inset CommandInset label
LatexCommand label
name "tab:frame-counter-handling"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
RX buffer RAM
\begin_inset CommandInset label
LatexCommand label
name "subsec:rx-buffer-RAM"

\end_inset


\end_layout

\begin_layout Standard
If 
\series bold
\shape italic
target_technology
\series default
\shape default
 = 0 (ASIC), clock for RX buffer RAM are gated if RX buffer RAM is not written
 nor read.
\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Section
Frame Filters
\begin_inset CommandInset label
LatexCommand label
name "subsec:Frame-Filters"

\end_inset


\end_layout

\begin_layout Description
File: frame_filters.vhd
\end_layout

\begin_layout Standard
Frame filters implement following functionality:
\end_layout

\begin_layout Itemize
Filter RX frames before storing to RX buffer based on CAN Identifier.
\end_layout

\begin_layout Itemize
Gate RX buffer commands when 
\color red
identifier
\color inherit
 does not pass Frame Filters.
\end_layout

\begin_layout Standard
Frame filters implement two types of filters: Bit filter and Range filter.
 There are three instances of Bit filter (A, B, C), and one instance of
 Range filter.
 Each instance is selectively synthesizable by 
\series bold
\shape italic
sup_filt_A/B/C
\series default
\shape default
 or 
\series bold
\shape italic
sup_range
\series default
\shape default
 generics.
 If filter is not synthesized, it is not taken into account during frame
 filtering.
 When no Frame filter is synthesized, all RX frames are stored to RX buffer
 and no frame is filtered out.
\end_layout

\begin_layout Standard
CAN frame passes Frame filters if received 
\color red
identifier
\color inherit
 passes at least one filter (logical OR).
 Filters are considered only when Acceptance filter mode is enabled (MODE[AFM]
 = '1').
 When Acceptance filter mode is disabled, all received frames are stored
 to RX buffer RAM.
\end_layout

\begin_layout Standard
Each filter can be configured to accept only given combination of Frame
 type and Identifier type via FILTER_CONTROL register.
 If received Frame type and Identifier type does not match accepted Frame
 type and Identifier type, it does not pass filter even if its identifier
 is matching.
 For description of filter operation reffer to 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-filter"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:range-filter"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 The logic equations in these tables follow C-like syntax with 
\begin_inset Quotes eld
\end_inset

&
\begin_inset Quotes erd
\end_inset

 meaning 
\begin_inset Quotes eld
\end_inset

logical AND
\begin_inset Quotes erd
\end_inset

 and 
\begin_inset Quotes eld
\end_inset

&&
\begin_inset Quotes erd
\end_inset

 meaning 
\begin_inset Quotes eld
\end_inset

boolean AND
\begin_inset Quotes erd
\end_inset

.
 (A,B) means concatenation of vectors A and B where A is MSB.
 Note that accepted combinations of Accepted Frame types / Identifier are
 one-hot coded in FILTER_CONTROL register and therefore any combination
 of these settings can be used.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="15line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="66line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Accepted Frame types / Identifier types
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Received Identifier type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Condition for frame to pass
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\begin_layout Plain Layout
RX_BASE = Received 
\color red
base identifier
\color inherit
, RX_EXT = Received 
\color red
identifier extension
\color inherit
, FILTER_X_MASK (A,B,C) = Filter mask, FILTER_X_VALUE (A,B,C) = Filter value,
 FR_TYPE = Received frame type (corresponds to 
\color red
FDF
\color inherit
 bit), ID_TYPE = Received identifier type (corresponds to 
\color red
IDE
\color inherit
 bit)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN 2.0 / Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
[(RX_BASE & FILTER_MASK(28:18)) == (FILTER_BASE(28:18) & FILTER_MASK(28:18))]
 && (FR_TYPE == CAN 2.0) && (ID_TYPE == Base)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD / Base
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
[(RX_BASE & FILTER_MASK(28:18)) == (FILTER_BASE(28:18) & FILTER_MASK(28:18))]
 && (FR_TYPE == CAN FD) && (ID_TYPE == Base)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN 2.0 / Extended
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
[(RX_BASE & FILTER_MASK(28:18)) == (FILTER_BASE(28:18) & FILTER_MASK(28:18))]
 && [(RX_EXT & FILTER_MASK(17:0)) == (FILTER_BASE(17:0) & FILTER_MASK(17:0))]
 && (FR_TYPE == CAN FD) && (ID_TYPE == Extended)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD / Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
[(RX_BASE & FILTER_MASK(28:18)) == (FILTER_BASE(28:18) & FILTER_MASK(28:18))]
 && [(RX_EXT & FILTER_MASK(17:0)) == (FILTER_BASE(17:0) & FILTER_MASK(17:0))]
 && (FR_TYPE == CAN FD) && (ID_TYPE == Extended)
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit filter operation
\begin_inset CommandInset label
LatexCommand label
name "tab:bit-filter"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="middle" width="15line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="66line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Accepted Frame types / Identifier types
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Received Identifier type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Condition for frame to pass
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\begin_layout Plain Layout
RX_BASE = Received 
\color red
base identifier
\color inherit
, RX_EXT = Received 
\color red
identifier extension
\color inherit
, FILTER_RAN_LOW = Lower filter threshold, FILTER_RAN_HIGH = Upper filter
 threshold, FR_TYPE = Received frame type (corresponds to 
\color red
FDF
\color inherit
 bit), ID_TYPE = Received identifier type (corresponds to 
\color red
IDE
\color inherit
 bit)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN 2.0 / Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
(RX_BASE >= FILTER_RAN_LOW(28:18)) && (RX_BASE <= FILTER_RAN_LOW(28:18)
 && (FR_TYPE == CAN 2.0) && (ID_TYPE == Base)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD / Base
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
(RX_BASE >= FILTER_RAN_LOW(28:18)) && (RX_BASE <= FILTER_RAN_LOW(28:18))
 && (FR_TYPE == CAN FD) && (ID_TYPE == Base)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN 2.0 / Extended
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
((RX_BASE, RX_EXT) >= FILTER_RAN_LOW(28:0)) && ((RX_BASE, RX_EXT) <= FILTER_RAN_
LOW(28:0)) && (FR_TYPE == CAN 2.0) && (ID_TYPE == Extended)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="3" alignment="left" valignment="middle" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN FD / Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Base
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
not accepted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multirow="4" alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Extended
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
((RX_BASE, RX_EXT) >= FILTER_RAN_LOW(28:0)) && ((RX_BASE, RX_EXT) <= FILTER_RAN_
LOW(28:0)) && (FR_TYPE == CAN FD) && (ID_TYPE == Extended)
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Range filter operation
\begin_inset CommandInset label
LatexCommand label
name "tab:range-filter"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
TXT buffer
\begin_inset CommandInset label
LatexCommand label
name "sec:TXT-Buffer"

\end_inset


\end_layout

\begin_layout Description
File: txt_buffer.vhd
\end_layout

\begin_layout Standard
TXT buffer implements following functionality:
\end_layout

\begin_layout Itemize
Stores single CAN frame for transmission in internal RAM memory.
\end_layout

\begin_layout Itemize
Manages access from HW and SW to its RAM memory.
\end_layout

\begin_layout Itemize
Provides status of frame transmission for SW.
\end_layout

\begin_layout Standard
Number of TXT buffers in CTU CAN FD is configurable at synthesis time by
 
\series bold
\shape italic
txt_buffer_count
\series default
\shape default
.
 Each TXT buffer contains 1 RAM memory.
 Each TXT buffer RAM is accessed by SW via Memory registers as described
 in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
 SW stores CAN frame to TXT buffer.
 For SW, TXT buffer RAM is write-only.
 TXT buffer RAM is also accessed by Protocol control FSM and TX arbitrator.
 TX arbitrator reads parts of CAN frame during TXT buffer valiation.
 Protocol control FSM reads data words from TXT buffer RAM as they are being
 transmitted on CAN bus.
 For Protocol control and TX arbitrator, TXT buffer is read-only.
 TXT buffer is managed by FSM which is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:txt-buffer-fsm"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 CAN frame format in TXT buffer is the same as in RX buffer, and it is described
 in 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:CAN-frame-format"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Each TXT buffer in CTU CAN FD has its own priority (configured by SW in
 TX_PRIORITY register).
 Based on priority, TX arbitratror selects TXT buffer which will be used
 for transmission (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:TX-Arbitrator"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_TXT_Buffer.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:txt-buffer-fsm"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TXT buffer commands
\begin_inset CommandInset label
LatexCommand label
name "subsec:TXT-Buffer-commands"

\end_inset


\end_layout

\begin_layout Standard
Two types of commands can be issued to TXT buffer: SW commands and HW commands.
 SW commands are issued by SW access to TX_COMMAND register.
 HW commands are issued by Protocol control FSM.
 Both command types are described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:txt-buffer-commands"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Since operation of SW and Protocol control FSM are not synchronized, HW
 and SW commands can occur simultaneously.
 Behavior in such cases is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:txt-buffer-simul-hw-sw-commands"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 If SW command is applied to TXT buffer FSM in state for which it is not
 valid, it has no effect.
 HW command is never applied in TXT buffer FSM state for which it is not
 valid (there are design assertions to check that).
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="8line%">
<column alignment="left" valignment="top" width="14line%">
<column alignment="left" valignment="top" width="56.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Command name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Command type 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Valid TXT buffer States
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When is command issued
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set ready
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Empty, TX OK, Aborted, TX failed
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW stored CAN frame to TXT buffer RAM and wants to transmit this frame.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set empty
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX OK, Aborted, TX failed
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW wants to move TXT buffer to its inital state after reset.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set abort
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Ready, TX in progress, Abort in progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW wants to abort transmission of a frame whose transmission has been previously
 requested by Set ready command.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Lock
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Ready
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM starts transmitting frame from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock - done
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in progress, Abort in progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control FSM successfully transmitted frame from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock - error
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in progress, Abort in progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Error frame
\color inherit
 occurred, Protocol control stops transmitting from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock - arbitration lost
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in progress, Abort in progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Arbitration
\color inherit
 was lost, Protocol control stops transmitting from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock failed
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in Progress, Abort in progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
A frame was re-transmitted number of times unsucesfully (either 
\color red
arbitration
\color inherit
 was lost or 
\color red
error frame
\color inherit
 occurred) and Retransmitt counter reached Retransmitt threshold.
 Frame transmission will not be attempted anymore.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer commands
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-commands"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="8line%">
<column alignment="left" valignment="top" width="8line%">
<column alignment="left" valignment="top" width="14line%">
<column alignment="left" valignment="top" width="58.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Command
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Command 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer state
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Result
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Lock
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set abort
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Ready
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer becomes 
\begin_inset Quotes eld
\end_inset

Abort in progress
\begin_inset Quotes erd
\end_inset

, Protocol control attempts to do do single transmission from thix TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock - done
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set abort
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in Progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is unlocked and becomes 
\begin_inset Quotes eld
\end_inset

TX OK
\begin_inset Quotes erd
\end_inset

 since transmission is successfull.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock - failed
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set abort
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in Progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is unlocked and becomes 
\begin_inset Quotes eld
\end_inset

TX failed
\begin_inset Quotes erd
\end_inset

 since transmission failed.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unlock - arbitration lost, error
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Set abort
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX in Progress
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is unlocked and becomes 
\begin_inset Quotes eld
\end_inset

Aborted
\begin_inset Quotes erd
\end_inset

.
 No more transmissions are attempted from this TXT buffer.
 In this case SW command has priority over HW command.
 Due to this, transmissions will not go on from thix TXT buffer.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer simultaneous HW/SW commands
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-simul-hw-sw-commands"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TXT buffer RAM
\end_layout

\begin_layout Description
File: txt_buffer_ram.vhd
\end_layout

\begin_layout Standard
TXT buffer RAM is written by SW (port A) and read by Protocol Control FSM
 (port B).
 TXT buffer RAM can be in one of two states: Unlocked and Locked.
 TXT buffer FSM states corresponding to Locked and Unlocked state of TXT
 buffer RAM are demonstrated in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:txt-buffer-fsm"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When TXT buffer is unlocked, it is not acessed by Protocol control (nor
 TX arbitrator) as there is no frame transmission/validation from this TXT
 buffer, and SW can write to TXT buffer via Memory registers.
 When TXT buffer is Locked, it was either marked as Ready, or validated
 by TX arbitrator, or transmission is in progress from this TXT buffer.
 When TXT buffer is locked, SW can not write to TXT buffer RAM, and attempts
 to write have no effect.
 
\end_layout

\begin_layout Subsection
TXT buffer - Transmission availability
\begin_inset CommandInset label
LatexCommand label
name "subsec:TXT-Buffer-tx-avail"

\end_inset


\end_layout

\begin_layout Standard
When TXT buffer FSM is in Ready state, it is 
\begin_inset Quotes eld
\end_inset

Available
\begin_inset Quotes erd
\end_inset

 for transmission from TX arbitrators point of view.
 However, if TXT buffer receives Set abort command, it become 
\begin_inset Quotes eld
\end_inset

Unavailable
\begin_inset Quotes erd
\end_inset

 for transmission in the same clock cycle as Set abort command is active
 (
\series bold
\shape italic
txtb_available
\series default
\shape default
 drops low).
 In this clock cycle, TXT buffer FSM is still in Ready state, and it will
 move to Aborted (or Abort in progress) in the following clock cycle.
 This combinatorial path from Set abort command to output of TXT buffer
 is necessary to avoid hazards on TXT buffer selection as explained in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:TX-Datapath-hazard"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Subsection
TXT buffer Parity
\end_layout

\begin_layout Standard
If enabled at synthesis time by 
\series bold
\shape italic
sup_parity
\series default
\shape default
 , each memory word of TXT buffer has additional parity bit.
 When the word is being written, the parity bit is computed and stored.
 When the word is being read by TX Arbitrator or Protocol Control FSM, the
 parity is computed again and compared with the read parity.
 If the computed parity and the read parity are not equal, the behavior
 is following:
\end_layout

\begin_layout Itemize
If the error is in Frame format, Identfier, Timestamp Low or Timestamp High
 words, the error occured as these 4 words were being read during TXT buffer
 validation.
 In this case, TXT buffer validation fails, and TXT buffer moves to Parity
 Error state.
 Transmission from this TXT buffer is never attempted.
\end_layout

\begin_layout Itemize
if the error is in some of the Data words, the parity error is detected
 as the word is read (during transmission of CAN frame).
 In this case, Protocol Control FSM transmits 
\color red
Error frame 
\color inherit
on the CAN bus, and TXT buffer moves to Parity Error state.
\end_layout

\begin_layout Subsection
TXT buffer - Use cases
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="27line%">
<column alignment="left" valignment="top" width="59line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action / State
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer RAM.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is in Empty state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW issues Set ready command.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer moves to Ready state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator validates TXT buffer for transmission and indicates this to
 Protocol control.
 On third bit of 
\color red
intermission
\color inherit
 or when bus is 
\color red
idle
\color inherit
, Protocol control issues Lock command, TXT buffer moves to TX inprogress
 and Protocol control starts transmission from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Frame transmission ends successfully and Protocol control issues Unlock
 - done command.
 TXT buffer moves to TX OK state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW reads state of TXT buffer and finds out that transmission ended succesfully.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer - sucessfull transmission
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-ok-transmission"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="35line%">
<column alignment="left" valignment="top" width="51line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action / State
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer RAM.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is in Empty state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW issues Set ready command.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer moves to Ready state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator validates TXT buffer for transmission and signals to Protocol
 control there is a valid TXT buffer for transmission.
 On third bit of Intermission or when bus is 
\color red
idle
\color inherit
, Protocol control issues Lock command, TXT buffer moves to TX in progress.
 Protocol control starts transmission from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
During transmission SW issues Set abort command to TXT buffer.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer moves to Abort in progress.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If 
\color red
error frame
\color inherit
 occurs or 
\color red
arbitration
\color inherit
 is lost, TXT buffer moves to Aborted state.
 If frame transmission finished succesfully, TXT buffer moves to TX OK state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW reads state of TXT buffer and finds out whether transmission was aborted
 or it ended succesfully.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer - Abort
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-abort"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="8" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="35line%">
<column alignment="left" valignment="top" width="51line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action / State
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer RAM.
 SW configures retransmitt limit to 5 and enables retransmitt limitation.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is in Empty state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW issues Set ready command.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer moves to Ready state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator validates TXT buffer for transmission and indicates available
 TXT buffer for transmission to Protocol control.
 On third bit of 
\color red
intermission
\color inherit
 or when bus is 
\color red
idle
\color inherit
, Protocol control issues Lock command, TXT buffer moves to TX in progress
 and Protocol control starts transmission from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
An 
\color red
error frame
\color inherit
 occurs or 
\color red
arbitration
\color inherit
 is lost, Protocol control issues Unlock - error or Unlock - arbitration
 lost command.
 TXT buffer moves to state Ready.
 Retransmitt counter is incremented by 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell multicolumn="1" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Steps 3-4 repeat until retransmitt counter reaches 5
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{cyan}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
On 5th retransmission (retransmitt counter = 5), error occurs.
 Protocol control issues Unlock - failed command.
 TXT buffer FSM moves to TX failed state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW reads state of TXT buffer and finds out that transmission failed.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer - transmission failed
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-tx-failed"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="35line%">
<column alignment="left" valignment="top" width="51line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action / State
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer RAM.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is in Empty state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW issues Set ready command.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer moves to Ready state.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW decides to abort transmission of this frame and issues Set abort command.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator validates TXT buffer for transmission and indicates available
 TXT buffer for transmission to Protocol control.
 On third bit of 
\color red
intermission
\color inherit
 or when bus is 
\color red
idle
\color inherit
, Protocol control issues Lock command.
 By coincidence, Set abort command (SW) and Lock command (HW) are active
 in the same clock cycle.
 TXT buffer moves to Abort in progress and Protocol control starts transmission
 from TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
An 
\color red
error frame
\color inherit
 occurs or 
\color red
arbitration
\color inherit
 is lost, Protocol control issues Unlock - error or Unlock - arbitration
 lost command.
 TXT buffer moves to state Aborted.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW reads state of TXT buffer and finds out that transmission was aborted.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer - Simultaneous Set abort and Lock
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-simul-abort-lock"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Section
TX arbitrator
\begin_inset CommandInset label
LatexCommand label
name "sec:TX-Arbitrator"

\end_inset


\end_layout

\begin_layout Description
File: tx_arbitrator.vhd
\end_layout

\begin_layout Standard
TX arbitrator implements following functionality:
\end_layout

\begin_layout Itemize
Picks TXT buffer for transmission.
\end_layout

\begin_layout Itemize
Loads CAN frame metadata and Identifier from TXT buffer, and provides them
 to CAN core for transmission.
\end_layout

\begin_layout Itemize
Checks parity of Metadata, Identifier and Timestamp words read from TXT
 buffer, and signals to TXT buffer that it contains corrupted data.
\end_layout

\begin_layout Itemize
Executes comparison of 
\series bold
\shape italic
timestamp
\series default
\shape default
 input with transmitted frame timestamp and determine moment of CAN frame
 transmission.
\end_layout

\begin_layout Itemize
Signals to CAN core that CAN frame was validated, and can be locked for
 transmission.
\end_layout

\begin_layout Itemize
Holds index of TXT buffer from which CAN core is actually transmitting.
\end_layout

\begin_layout Itemize
Detects change of TXT buffer between two consecutive transmissions.
\end_layout

\begin_layout Standard
TX arbitrator block diagram is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:tx-arbitrator-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_TX_Arbitrator.pdf
	lyxscale 20
	scale 71

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:tx-arbitrator-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TXT buffer validation process
\end_layout

\begin_layout Standard
With regards to processing by TX arbitrator, each TXT buffer can be in one
 of states described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-arbitrator-buffer-processing"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 TXT buffer validation process starts when Priority decoder picks highest
 priority Available TXT buffer (such TXT buffer becomes 
\begin_inset Quotes eld
\end_inset

Selected
\begin_inset Quotes erd
\end_inset

) for transmission (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Priority-decoder"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 Validation process is described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-arbitrator-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 An FSM controlling the selection is shown in 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:fsm-tx-arbitrator"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Note each state of TXT buffer FSM which is part of TXT buffer validation
 lasts for two clock cycles due to wait state.
 Such wait state is inserted to cover delay of TXT buffer RAM.
\end_layout

\begin_layout Standard
If index of Selected TXT buffer changes (due to another higher priority
 TXT buffer becoming Ready, or change of TXT buffers priorities) during
 validation process, or after validation process was finished (TX arbitrator
 FSM is in Validated state), TXT buffer validation process restarts with
 newly Selected TXT buffer.
\end_layout

\begin_layout Standard
If Validated TXT buffer suddenly becomes Unavailable (due to Set abort SW
 command), TX arbitrator signals immediately (in the same clock cycle) to
 Protocol control FSM that there is no Validated TXT buffer (this is done
 to avoid control hazards on TX frame datapath, and it is further explained
 in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:TX-Datapath-hazard"
plural "false"
caps "false"
noprefix "false"

\end_inset

) and TX arbitrator FSM moves to Idle state.
 Several use-cases are explained in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-arbitrator-usecase-1"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:tx-arbitrator-use-case-2"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
When there is a Validated TXT buffer, Protocol control FSM issues Lock command
 during bus 
\color red
idle
\color inherit
, or third bit of 
\color red
intermission
\color inherit
.
 In such case, TX arbitrator goes to Locked state and TXT buffer becomes
 Used from TX arbitrators point of view (TXT buffer FSM itself goes to TX
 in progress).
 Protocol control then transmitts the frame from this TXT buffer, and upon
 the end of transmission issues Unlock command.
 TXT buffer then becomes either Available or Unavailable (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:TXT-Buffer-commands"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
\end_layout

\begin_layout Standard
If during TXT buffer validation process, TX Arbitrator detects parity error
 in Metadata, Identifier or Timestamp words, it immediately aborts validation
 of such TXT buffer, and signals this to TXT buffer.
 If TXT buffer is 
\begin_inset Quotes eld
\end_inset

Used
\begin_inset Quotes erd
\end_inset

 (transmission is being executed from it), and TX Arbitrator detects that
 parity is corrupted on a data word which is being transmitted, it also
 signals this to TXT buffer.
 
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_TX_Arbitrator.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:fsm-tx-arbitrator"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
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\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="83.5line%">
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<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
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Filter name
\begin_inset ERT
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\begin_layout Plain Layout


\backslash
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\end_layout

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<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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\begin_inset ERT
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\begin_layout Plain Layout


\backslash
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\end_layout

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<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Unavailable
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is Unavailable when it is not Available for transmission as defined
 in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:TXT-Buffer-tx-avail"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Such a TXT buffer is ignored by TX arbitrator.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Available
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is Available when it is Available for transmission as defined
 in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:TXT-Buffer-tx-avail"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Selected
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is Selected when it is Available with highest priority out of
 all Available TXT buffers.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Validated
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is Validated when it is Available for transmission, its Timestamp
 comparison has been executed and Metadata from TXT buffer RAM (Frame format
 word) has been loaded to capture registers for CAN core.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

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Used
\end_layout

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</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer is Used after CAN core issues Lock command on Validated TXT buffer
 and is transmitting from this TXT buffer.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator - TXT buffer processing
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-arbitrator-buffer-processing"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="13" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="56line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

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\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
External action (SW or external components)
\begin_inset ERT
status open

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\backslash
cellcolor{gray}
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\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No TXT buffer is Available.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer 1 and issues Set ready command to this TXT buffer.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 FSM goes to Ready state is and therefore Available for TX arbitrato
r.
 As this is only TXT buffer which is Available, Priority decoder selects
 it as highest priority Available TXT buffer.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator FSM loads Lower timestamp word from TXT buffer 1 RAM, and
 stores it to auxiliarly register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator FSM loads Upper timestamp word from TXT buffer 1 RAM and executes
 comparison of 
\series bold
\shape italic
timestamp
\series default
\shape default
 input and timestamp of CAN frame in TXT buffer 1 (Lower word is in auxiliarly
 register and Upper word is on output of TXT buffer 1 RAM).
 When 
\series bold
\shape italic
timestamp
\series default
\shape default
 is lower than timestamp of CAN frame in TXT buffer 1, TX arbitrator waits,
 otherwise it proceeds to step 5.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
\shape italic
timestamp
\series default
\shape default
 is incrementing (as it counts running time within a system) and it reaches
 value of CAN frame timestamp in TXT buffer 1.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator detects 
\series bold
\shape italic
timestamp
\series default
\shape default
 input is now higher than timestamp of CAN frame in selected TXT buffer.
 At this moment TX arbitrator proceeds with frame validation.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator FSM loads TX frame metadata from TXT buffer 1 RAM (Frame format
 word) to double-buffer registers.
 These are not visible to CAN Core, they hold metadata internally.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator FSM loads TX frame identifier from TXT buffer 1 RAM (Identifier
 word) to Identifier capture register.
 At the same clock cycle, TX arbitrator FSM loads metadata from double-buffer
 registers to capture registers on output of TX Arbitrator.
 Reffer to 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:Metadata-double-buffering"
plural "false"
caps "false"
noprefix "false"

\end_inset

 for explanation.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 becomes 
\begin_inset Quotes eld
\end_inset

validated
\begin_inset Quotes erd
\end_inset

 and TXT arbitrator signals that there is a valid TX frame for transmission
 to CAN core.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When Protocol control FSM is in 
\color red
sample point
\color inherit
 of third bit of 
\color red
intermission
\color inherit
 or bus 
\color red
idle
\color inherit
, it issues Lock command to TXT buffer 1 (TXT buffer 1 becomes Used, TXT
 buffer FSM moves to TX in progress state) and TX arbitrator becomes Locked.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator is Locked and it is waiting for Unlock command.
 No TXT buffer validation is in progress.
 If another higher priority TXT buffer became Available this has no effect
 as frame transmission is already in progress.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control transmitts frame from TXT buffer 1, and issues Unlock -
 done command to TXT buffer 1 (TXT buffer 1 becomes Unavailable and TXT
 buffer FSM moves to TX OK).
 Since TXT buffer 1 was only TXT buffer which was Available before the transmiss
ion, now there is no TXT buffer which is Available.
 Therefore no TXT buffer is Selected, and no TXT buffer validation is in
 progress.
 TX arbitrator signals there is no Validated TXT buffer to CAN Core.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
11
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW reads state of TXT buffer 1 and finds out whether transmission was aborted
 or it ended succesfully.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator operation
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-arbitrator-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="56line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
External action (SW or external components)
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW configures priority 1 to TXT buffer 1 and priority 2 to TXT buffer 2.
 SW fills TXT buffer 1 and TXT buffer 2 by CAN frames.
 SW issues Set ready command to TXT buffer 1.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 FSM goes to Ready state and therefore TXT buffer 1 becomes
 Available from TX arbitrators point of view.
 Since this is only Available TXT buffer, it becomes Selected.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator performs validation process (loads timestamp words, executes
 timestamp comparison, loads metadata and identifier) and TXT buffer 1 becomes
 Validated.
 TX arbitrator signals to CAN core that there is validated TXT buffer for
 transmission.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Issues Set ready command to TXT buffer 2.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 2 FSM goes to Ready state and therefore TXT buffer 2 becomes
 Available from TX arbitrators point of view.
 As TXT buffer 2 has higher priority than TXT buffer 1, TXT buffer 2 becomes
 Selected by Priority decoder.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer validation process restarts with TXT buffer 2.
 During validation of TXT buffer 2, TXT buffer 1 remains Validated (TXT
 buffer 1 is still Available).
 If during validation process of TXT buffer 2, Protocol control issued HW
 Lock command, transmission would still start from TXT buffer 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator finishes validation process (loads timestamp words, executes
 timestamp comparison, loads metadata) of TXT buffer 2.
 At the end, TXT buffer 2 becomes Validated, and TXT buffer 1 (which was
 Validated till now) becomes Available.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control issues Lock command and since TXT bufer 2 is now Validated,
 transmission starts from TXT buffer 2.
 TX arbitrator becomes Locked.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator - use-case 1
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-arbitrator-usecase-1"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Description
Note: The implementation performs validation of a TXT buffer while another
 TXT buffer is still Validated.
 Only when validation process is finished, index of Validated TXT buffer
 will be changed to the new TXT buffer.
 The reason is following: If TXT buffer is validated, and SW decides to
 issue Set ready to another TXT buffer which is higher priority, Lock command
 might arrive just slightly after this moment (SW and Protocol control have
 no synchronisation).
 If first TXT buffer did not remain validated during validation process
 of new TXT buffer, 
\series bold
\shape italic
tran_frame_valid
\series default
\shape default
 signal would drop low before the validation process of second TXT buffer
 is finished.
 This would cause that for short time, Protocol control would not have any
 TXT buffer available for transmission, while actually two TXT buffers are
 in Ready state.
 This effect is undesirable.
\end_layout

\begin_layout Description
Note: Due to meta-data double buffering, validated TXT buffer is swapped
 atomically (TXT buffer index, identifer and loaded metadata) from Protocol
 control point of view.
 Thus it can never happen that inconsistent frame is transmitted (e.g.
 metadata from one TXT buffer and data words from another TXT buffer).
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="35line%">
<column alignment="left" valignment="top" width="51line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
External action (SW or external components)
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW configures TXT buffer 1 priority to 1, and TXT buffer 2 priority to 2.
 SW fills TXT buffer 1 and TXT buffer 2 RAMs by CAN frames.
 SW Issues Set ready command to TXT buffer 1 and TXT buffer 2 simultaneously.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffers 1 and 2 become Available, and TXT buffer 2 becomes Selected
 because it has higher priority than TXT buffer 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator performs TXT buffer 2 validation process (loads timestamp
 words, executes timestamp comparison, loads metadata and identifier) and
 TXT buffer 2 becomes Validated.
 TX arbitrator signals to CAN core that there is Validated TXT buffer for
 transmission.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW Issues Set abort command to TXT buffer 2.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 2 which is now Validated becomes Unavailable.
 TX arbitrator immediately (in the same clock cycle) signals to CAN core
 that no TXT buffer is available for transmission (
\series bold
\shape italic
tran_frame_valid
\series default
\shape default
 signal drops low).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Since TXT buffer 1 is now only Available TXT buffer, it becomes Selected.
\end_layout

\begin_layout Plain Layout
TX arbitrator proceeds with validation of TXT buffer 1, and upon its end
 TXT buffer 1 becomes Validated.
 TX arbitrator signals that there is a frame available for transmission.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator - use-case 2
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-arbitrator-use-case-2"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Description
Note: This behaviour is necessary, since TXT buffer which is Validated suddenly
 becomes Unavailable due to Set Abort command.
 If 
\series bold
\shape italic
tran_frame_valid
\series default
\shape default
 signal did not drop low immediately, it could happend that Protocol control
 would issue Lock command on a TXT buffer which was Unavailable (in Aborted
 state).
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="56line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
External action (SW or external components)
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW stores a frame to a TXT buffer 1 and issues Set ready command.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 becomes available from TX Arbitrator point of view.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX Arbitrator starts validating TXT buffer 1.
 It reads out Metadata, Identifier, Timestamp Low/High words.
 During each of these words, it checks that parity of word being read is
 correct.
 If not, it stops validation of this TXT buffer, and it signals this to
 TXT buffer 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 moves to Parity Error state.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TX arbitrator - use-case 3
\begin_inset CommandInset label
LatexCommand label
name "tab:tx-arbitrator-usecase-1-3"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Priority decoder
\begin_inset CommandInset label
LatexCommand label
name "subsec:Priority-decoder"

\end_inset


\end_layout

\begin_layout Description
File: priority_decoder.vhd
\end_layout

\begin_layout Standard
Priority decoder selects highest priority TXT buffer from all Available
 TXT buffers.
 Such TXT buffer becomes Selected.
 Priority of TXT buffers is given by SW (TX_PRIORITY register).
 If no TXT buffer is Available, Priority decoder signals it on its output,
 and no TXT buffer is Selected (TXT buffer validation does not start).
 If two Available TXT buffers have equal priority, TXT buffer with lower
 index is selected.
 Priority decoder provides index of Selected TXT buffer on its output.
\end_layout

\begin_layout Standard
Priority decoder is implemented as comparator tree with 3 levels (see Figure
 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:priority-decoder-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 Each level contains so called 
\begin_inset Quotes eld
\end_inset

decoder cells
\begin_inset Quotes erd
\end_inset

.
 Decoder cell selects higher priority TXT buffer from two TXT buffers.
 Each decoder cell behaves like so:
\end_layout

\begin_layout Itemize
When only one of the two TXT buffers is Available it is automatically selected,
 its index is propagated as winner of comparison and 
\begin_inset Quotes eld
\end_inset

Available
\begin_inset Quotes erd
\end_inset

 output of this decoder cell is high.
\end_layout

\begin_layout Itemize
When no TXT buffer input is Available, 
\series bold
\shape italic
\color black
output_valid
\series default
\shape default
\color inherit
 signal is low.
\end_layout

\begin_layout Itemize
When both TXT buffer inputs are Available, 
\series bold
\shape italic
\color black
output_valid
\series default
\shape default
\color inherit
 signal is high and index TXT buffer with higher priority is propagated
 as winner.
\end_layout

\begin_layout Standard
Priority decoder supports up to 8 input TXT buffers.
 If less than 8 TXT buffers are configured (see 
\series bold
\shape italic
txt_buffer_count
\series default
\shape default
), unused inputs are tied to zeroes.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_priority_decoder.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Priority decoder block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:priority-decoder-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TXT buffer change between transmissions
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="10" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="35line%">
<column alignment="left" valignment="top" width="51line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
HW action / State
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer 1 RAM.
 SW enables retransmitt limitation and configures Retransmitt limit to 5.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 FSM is in Empty State.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW issues Set ready command to TXT buffer 1.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 1 FSM moves to Ready state.
 TXT buffer 1 becomes Available from TX arbitrators point of view.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator performs validatation and TXT buffer 1 becomes Validated,
 TX arbitrator signals this to CAN core.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN core issues Lock command and starts transmitting from TXT buffer 1.
 TXT buffer 1 becomes Used and TXT buffer 1 FSM goes to TX in progress state
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
An 
\color red
error frame
\color inherit
 occurs or 
\color red
arbitration
\color inherit
 is lost.
 Protocol control signals Unlock - 
\color red
arbitration
\color inherit
 lost or Unlock - error frame
\begin_inset Quotes erd
\end_inset

 commands.
 TXT buffer 1 becomes Unavailable , TXT buffer 1 FSM moves to Ready and
 Retransmitt counter is incremented to 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SW fills TXT buffer RAM 2.
 SW Issues Set ready command to TXT buffer 2.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT buffer 2 moves to Ready state.
 Lets assume TXT buffer 2 has higher priority than TXT buffer 1.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Now there are two Available TXT buffers (1 and 2).
 TXT buffer 2 becomes Selected by Priority decoder because it has higher
 priority.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX arbitrator performs validation and TXT buffer 2 becomes Validated, TX
 arbitrator signals this to CAN core.
 
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
8
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN core issues Lock command, TXT buffer 2 becomes Used (transmission starts
 by CAN core).
 At this moment Retransmitt counter is cleared because TXT buffer used for
 current transmission (TXT buffer 2) is different from the one for previous
 transmission (TXT buffer 1).
 (counting retransmissions on TXT buffer 2 shall not include one previous
 failed transmission from TXT buffer 1, because it is different CAN frame
 being transmitted).
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Selected TXT buffer changed between transmissions
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-change"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TX Arbitrator corner-cases
\end_layout

\begin_layout Standard
TX arbitrator must react on following events which are all not synchronized:
\end_layout

\begin_layout Itemize
Change of TXT buffer priorities by SW -> possibly change of Selected TXT
 buffer.
\end_layout

\begin_layout Itemize
Change of TXT buffer state (due to SW commands) -> possibly change of Selected
 TXT buffer.
\end_layout

\begin_layout Itemize
Lock command from Protocol control.
\end_layout

\begin_layout Standard
Handling of these events is resolved like so:
\end_layout

\begin_layout Itemize
Lock command shall never occur when TX Arbitrator FSM is Idle.
\end_layout

\begin_layout Itemize
Unlock command shall never occur when TX Arbitrator FSM is not Locked.
\end_layout

\begin_layout Itemize
Lock command shall only occur when there is TXT buffer available for transmissio
n, or when it was available for transmission in previous clock cycle.
 It might happend, that Lock command and Set abort command are active simultaneo
usly.
 Due to Set abort command, it might be that only Available TXT buffer becomes
 immediately unavailable, therefore Lock command is active when no Available
 TXT buffer is signalled.
 This is OK since TXT buffer FSM resolves simultaneous Set abort and Lock
 command.
\end_layout

\begin_layout Itemize
Lock command occurs at the same time as Selected TXT buffer is changed.
 Lock command shall have priority, and TX Arbitrator FSM shall become Locked.
\end_layout

\begin_layout Itemize
TXT buffer validation process is about to be finished, but Lock command
 occurs.
 Lock command shall have priority, TX Arbitrator FSM shall become Locked
 and Metadata, Identifier capture registers shall not be preloaded!
\end_layout

\begin_layout Subsection
TXT buffer addressing
\end_layout

\begin_layout Standard
During TXT buffer validation process, TX arbitrator is accessing TXT buffer
 memories and loads Frame format, Identifier, Timestamp low and Timestamp
 High words, therefore TXT buffer RAM address on port B is given by TX arbitrato
r FSM.
\end_layout

\begin_layout Standard
During transmission when TX arbitrator is Locked, TX arbitrator holds index
 of Used TXT buffer.
 During this time, Protocol control FSM provides address of memory word
 from which it reads relevant data word for transmission.
 TX arbitrator uses this address to drive TXT buffer address and index of
 Used TXT buffer to multiplex read data.
 Data memory words (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:CAN-frame-format"
plural "false"
caps "false"
noprefix "false"

\end_inset

) are addressed during transmission of 
\color red
data field
\color inherit
 and Protocol control transmitts value of
\color red
 data field
\color inherit
 from these memory words.
 Each next 4 bytes of 
\color red
data field
\color inherit
 correspond to one memory word in TXT buffer RAM.
 From output of TXT buffer RAM, this memory word is loaded to TX shift register
 and transmitted from there (see 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:TX-Shift-Register"
plural "false"
caps "false"
noprefix "false"

\end_inset

).
 Therefore Protocol control provides address of data word with sufficient
 reserve to cover latency of TXT buffer RAM as is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:txt-buffer-ram-addressing"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Metadata and Identifier for transmission are available from capture registers
 in TX arbitrator which were loaded during TXT buffer validation process.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="25line%">
<column alignment="left" valignment="top" width="46line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN frame field 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory word in TXT buffer addressed by Protocol control 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Meaning of data loaded to TX shift register
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
DLC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data word 0
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
data field
\color inherit
 bytes 0 ..
 3
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
data field
\color inherit
 byte N * 4 - 1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data word N + 1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
data field
\color inherit
 bytes (N * 4) to (N + 1) * 4
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
TXT buffer RAM adressing during transmission
\begin_inset CommandInset label
LatexCommand label
name "tab:txt-buffer-ram-addressing"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TXT buffer RAM access
\end_layout

\begin_layout Standard
TXT buffer RAM has clock gating implemented if 
\series bold
\shape italic
target_technology 
\series default
\shape default
= 0 (ASIC).
 In such case, clocks are enabled only when there are write (by user) or
 read accesses (by TX Arbitrator or Protocol control FSM) to RAM.
 If TX Arbitrator is performing TXT buffer validation process, the clocks
 are ungated during this process since TX Arbitrator is reading metadata
 words from TXT buffer RAM.
 If Protocol control FSM is reading data words (during transmission of data
 field), TXT buffer RAM clocks are ungated when new word shall be read (when
 read pointer is updated by Protocol control FSM).
\end_layout

\begin_layout Subsection
TX frame timestamp comparison
\end_layout

\begin_layout Standard
Part of TXT buffer validation process is comparison of 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input with timestamp of CAN frame in TXT buffer which is currently being
 validated.
 If 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input is lower than timestamp of CAN frame in currently validated TXT buffer,
 validation process is paused.
 When 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input is equal to, or higher than timestamp of CAN frame in currently validated
 TXT buffer, TXT buffer validation proceeds.
 If during this time index of Selected TXT buffer changes, validation process
 is restarted.
\end_layout

\begin_layout Standard
Comparison of timestamps provides the Time triggered transmission functionality
 as is described in 9.2 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
 Only when 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input passes (desired moment of transmission passes), TXT buffer is admited
 for transmission to CAN core.
 This does not mean that CAN core will transmit the frame immediately! CAN
 core will transmitt such frame in nearest 
\color red
bus idle
\color inherit
, or when it samples dominant bit during third bit of 
\color red
intermission
\color inherit
.
 Since TXT buffer validation process takes 6 clock cycles, 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input must reach TX frame timestamp at latest 6 clock cycles of System
 clock before 
\color red
sample point
\color inherit
 of a bit to be considered for transmission from following bit on CAN bus.
 Mismatch between the time when frame validation finishes due to transmitted
 frame timestamp passing, and 
\color red
sample point
\color inherit
 of 
\color red
SOF
\color inherit
 bit can be up to two bit times as is demonstrated in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:time-triggered-transmission"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 This situation can be avoided if change of time is synchronized in a system
 with sufficiently large period of counting on 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input (close to Bit time period).
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/time_triggered_transmission.pdf
	lyxscale 20
	scale 48

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Time triggered transmission
\begin_inset CommandInset label
LatexCommand label
name "fig:time-triggered-transmission"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Consider having two TX frames with timestamps 10 (in TXT buffer 1) and 50
 (in TXT buffer 2).
 Lets assume that TXT buffer 2 has higher priority, and it is therefore
 Selected and validation process is in progress.
 It finishes its validation when 
\series bold
\shape italic
\color black
timestamp
\series default
\shape default
\color inherit
 input becomes 50.
 Although CAN frame in TXT buffer 1 has lower timestamp, it is transmitted
 after frame from TXT buffer 2 because TXT buffer 2 has higher priority!
 Therefore TXT buffer priority is at any moment considered first during
 TXT buffer selection and CAN frame timestamp is considered only from Selected
 TXT buffer.
\end_layout

\begin_layout Subsection
Lock and Unlock commands
\end_layout

\begin_layout Standard
Protocol control FSM issues Lock command in third bit of 
\color red
intermission
\color inherit
 (when it samples 
\color red
dominant
\color inherit
 bit) or during 
\color red
bus idle
\color inherit
 when there is a Validated TXT buffer available.
 In such case, CTU CAN FD becomes 
\color red
transmitter
\color inherit
 of the following CAN frame.
 After Lock command, TX arbitrator becomes Locked.
 If there is no TXT buffer Validated so far and TXT buffer becomes Validated
 just slightly after Protocol control samples 
\color red
dominant
\color inherit
 bit during third bit of 
\color red
intermission
\color inherit
 or 
\color red
bus idle
\color inherit
, unit becomes 
\color red
receiver
\color inherit
 and frame from Validated TXT buffer is not transmitted.
 If 
\color red
suspend transmission
\color inherit
 field is transmitted and Protocol control samples 
\color red
dominant
\color inherit
 bit, Protocol control does not issue Lock command and becomes 
\color red
receiver
\color inherit
 of following frame.
\end_layout

\begin_layout Subsection
Metadata double-buffering
\begin_inset CommandInset label
LatexCommand label
name "subsec:Metadata-double-buffering"

\end_inset


\end_layout

\begin_layout Standard
During TXT buffer validation process, TX arbitrator first reads Frame format
 word from TXT buffer RAM and stores it in internal registers which are
 invisible to CAN core.
 In the next step TX arbitrator reads Identifier word from TXT buffer RAM
 and stores it to capture register which is available to CAN core.
 At the same time internal registers with metadata are moved to capture
 registers for metadata.
 Therefore, reading of metadata from TXT buffer RAM is double-buffered.
 Both identifier and metadata available for CAN core are changed at once
 (atomically), therefore it will never happend that Identifier in capture
 registers corresponds to different CAN frame than metadata in capture registers.
 This is necessary as when there is Validated TXT buffer, another TXT buffer
 validation process can be in progress.
 In change was not atomic, CAN core could issue Lock command and transmitt
 e.g.
 ID from TXT buffer 1 and metadata from TXT buffer 2.
\end_layout

\begin_layout Subsection
TX datapath hazard protection
\begin_inset CommandInset label
LatexCommand label
name "subsec:TX-Datapath-hazard"

\end_inset


\end_layout

\begin_layout Standard
TX frame datapath (TX arbitrator + TXT buffers) are both manipulated by
 SW and HW commands simultaneously.
 This fact opens question of hazards susceptibility.
 Such a hazard would occur, when e.g.
 TXT buffer FSM moved to Aborted state after Set abort command, but Protocol
 control FSM still managed to issue Lock command and start transmission
 from this TXT buffer.
 In such case, Protocol control FSM would transmitt from TXT buffer which
 is Aborted (and therefore content of its RAM can be modified by SW).
 Due to combinatorial path between Set abort and indication of Validated
 TXT buffer, it never happends that when Set abort command is issued to
 a TXT buffer, Protocol control FSM would issue Lock command, therefore
 this situation will never occur.
 The relevant combinatorial path is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:tx-data-path-hazards"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/Hazard_prevention_logic.pdf
	lyxscale 20
	scale 90

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TX datapath hazard protection
\begin_inset CommandInset label
LatexCommand label
name "fig:tx-data-path-hazards"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TX Abort + Retransmitt clear
\end_layout

\begin_layout Standard

\color blue
TODO: This feature is not yet designed! If TXT buffer which is currently
 Validated or Used becomes 
\begin_inset Quotes eld
\end_inset

Aborted
\begin_inset Quotes erd
\end_inset

, then retransmitt counter should be also cleared.
 It can happen that user will abort buffer, replace CAN frame within this
 buffer and put ready again.
 In such a case, retransmitt counter should count only retransmissions of
 new frame! This would become epecially important if we went for generic
 amount of TXT buffers! If config with only 1 TXT buffer was used, then
 any abort in actual implementation leaves retransmitt counter untouched
 and any new frame would start with this value of retransmitt counter...
 This could be implemented like so: If TXT buffer FSM moves to Aborted,
 it gives a signal.
 If last TXT buffer that was used for transmission (not Selected one because
 when abort is applied on TXT buffer, it will not be Selected!), is equal
 to index of TXT buffer that just moved to Abort, then retransmitt counter
 will be cleared.
 This still needs to be evaluated.
\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Section
Interrupt Manager
\end_layout

\begin_layout Description
File: int_manager.vhd
\end_layout

\begin_layout Standard
Interrupt manager implements following functionality:
\end_layout

\begin_layout Itemize
Captures occurence of events/conditions within CTU CAN FD to Interrupt status
 register.
\end_layout

\begin_layout Itemize
Interrupt masking and enabling.
\end_layout

\begin_layout Itemize
Generates of level-based Interrupt output.
\end_layout

\begin_layout Standard
Occurence of events within CTU CAN FD is captured to Interrupt status register
 (INT_STAT) register when corresponding interrupt is unmasked.
 When Interrupt is masked, correponding event is ignored.
 Interrupt mask is set by writing logic 1 to corresponding bit of INT_MASK_SET
 register.
 Interrupt mask is cleared by writing logic 1 to corresponding bit of INT_MASK_C
LR register.
 When a bit in Interrupt status register is set, it causes 
\series bold
\shape italic
int
\series default
\shape default
 output of CTU CAN FD to go high when this interrupt is enabled.
 A bit in Interrupt status register is cleared by writing logic 1 to correspondi
ng bit in INT_STAT register.
 Value of 
\series bold
\shape italic
int
\series default
\shape default
 output is given by logical OR of all enabled interrupts which have Interrupt
 status equal to logic 1.
 Interrupt output is registered to be glitch free.
 Interrupt is enabled by writing logic 1 to corresponding bit of INT_ENA_SET
 register.
 Interrupt is disabled by writing logic 1 to corresponding bit of INT_ENA_CLR
 register.
 When Interrupt status shall be set at the same clock cycle by an internal
 event of CTU CAN FD and cleared by write to INT_STAT register, Interrupt
 will be set (set has priority over clear).
 Block diagram of single interrupt datapath is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:int-single-datapath"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Available types of Interrupts are described in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-2"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/Interrupt_single.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Single interrupt datapath
\begin_inset CommandInset label
LatexCommand label
name "fig:int-single-datapath"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Section
Prescaler
\end_layout

\begin_layout Description
File: prescaler.vhd
\end_layout

\begin_layout Standard
Prescaler implements following functionality:
\end_layout

\begin_layout Itemize
Measures
\color red
 Time quanta
\color inherit
 (for both 
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
 
\color red
bit rates
\color inherit
).
\end_layout

\begin_layout Itemize
Measures Bit segments (
\color red
Sync_Seg
\color inherit
, 
\color red
Prop_Seg
\color inherit
, 
\color red
Phase_Seg1
\color inherit
 and 
\color red
Phase_Seg2
\color inherit
).
\end_layout

\begin_layout Itemize

\color red
Hard synchronisation
\color inherit
 and 
\color red
resynchronisation
\color inherit
 as defined in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Itemize
Checks if edge is valid for 
\color red
synchronisation
\color inherit
 (only one edge between two 
\color red
sample points
\color inherit
).
\end_layout

\begin_layout Itemize
Generates TX trigger and RX triggers for each stage of pipeline.
\end_layout

\begin_layout Itemize
Switches between 
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
 
\color red
bit rates
\color inherit
.
\end_layout

\begin_layout Standard
Prescaler block diagram is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:prescaler-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_Prescaler.pdf
	lyxscale 20
	scale 60

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Prescaler block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:prescaler-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
CAN FD standard (
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

) distuiguishes two 
\color red
bit rates
\color inherit
: 
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
.
 CTU CAN FD implementation distuighushes 3 
\color red
bit rate
\color inherit
 types as shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ctu-can-fd-bit-rate-types"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Protocol Control FSM configures correct 
\color red
bit rate
\color inherit
 in according parts of CAN frame as explained in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="61line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit rate type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Corresponding 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

 
\color red
bit rate
\color inherit

\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Nominal
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Nominal
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Nominal bit rate
\color inherit
 for both 
\color red
transmitter
\color inherit
 and 
\color red
receiver
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data bit rate
\color inherit
 for 
\color red
receiver
\color inherit
 of CAN FD frame.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Secondary
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Data 
\color red
bit rate
\color inherit
 for 
\color red
transmitter
\color inherit
 of CAN FD frame.
 
\color red
Secondary sampling point
\color inherit
 is used to detect 
\color red
bit error
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit-Rate types
\begin_inset CommandInset label
LatexCommand label
name "tab:ctu-can-fd-bit-rate-types"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Prescaler contains separate logic for both 
\color red
bit
\color inherit
 
\color red
rates
\color inherit
 (
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
).
 Logic for Secondary is the same as for Data.
 During bits where 
\color red
bit rate
\color inherit
 is switched, logic for both bit rates is enabled simultaneously, otherwise
 only logic for actual 
\color red
bit rate
\color inherit
 is enabled.
\end_layout

\begin_layout Subsection
Bit rate configuration
\begin_inset CommandInset label
LatexCommand label
name "subsec:Bit-Rate-configuration"

\end_inset


\end_layout

\begin_layout Standard
Bit rates (
\color red
nominal and data
\color inherit
) are configured by SW when CTU CAN FD is disabled (SETTINGS[ENA] = '0')
 in registers BTR (
\color red
nominal
\color inherit
) and BTR_FD (
\color red
data
\color inherit
).
 BTR and BTR_FD registers are writable only when SETTINGS[ENA]='0', otherwise
 write access to these registers has no effect.
 Timing parameters for each
\color red
 bit rate
\color inherit
 are listed in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ctu-can-fd-bit-rate-config"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="56line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Parameter name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Abbreviation
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit rate prescaler
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
BRP
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Time quanta
\color inherit
 = Bit rate prescaler * System clock period
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synchronisation segment length
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Length of Synchronisation segment is always 1 
\color red
time quanta
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Propagation segment length
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
PROP
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Configured in multiples of 
\color red
time quanta
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Phase 1 segment length
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
PH1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Configured in multiples of 
\color red
time quanta
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Phase 2 segment length
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
PH2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Configured in multiples of 
\color red
time quanta
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synchronisation jump width
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SJW
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Configured in multiples of 
\color red
time quanta
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
CTU CAN FD bit rate configuration
\begin_inset CommandInset label
LatexCommand label
name "tab:ctu-can-fd-bit-rate-config"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Bit time counters
\end_layout

\begin_layout Description
File: bit_time_counters.vhd
\end_layout

\begin_layout Standard
Bit time counters module contains two counters: Time quanta counter and
 Segment counter.
 There are two intstances of Bit time counters module, 
\color red
nominal
\color inherit
 (NBTCM) and 
\color red
data
\color inherit
 (DBTCM).
\end_layout

\begin_layout Standard
Time quanta counter measures length of 
\color red
time quanta
\color inherit
, and provides information that 
\color red
time quanta
\color inherit
 has elapsed (
\series bold
\shape italic
tq_edge
\color black
_nbt
\series default
\shape default
\color inherit
/
\series bold
\shape italic
\color black
dbt
\series default
\shape default
\color inherit
=1).
 
\color red
Time quanta
\color inherit
 has elapsed when Time quanta counter is equal to Bit rate prescaler (therefore
 dividing the frequency of System clock by Bit rate prescaler).
 When Bit rate prescaler is 1,
\series bold
\shape italic
 tq_edge
\color black
_nbt
\series default
\shape default
\color inherit
/
\series bold
\shape italic
\color black
dbt
\series default
\shape default
\color inherit
 is active continously, Otherwise it is active one clock cycle at the end
 of 
\color red
time quanta
\color inherit
.
 When Bit rate prescaler is 1, 
\color red
time quanta
\color inherit
 is equal to System clock period, and Time quanta counter is not running.
\end_layout

\begin_layout Standard
Segment counter counts number of
\color red
 time quanta
\color inherit
 of actual bit segment (counts only when 
\series bold
\shape italic
tq_edge
\color black
_nbt
\series default
\shape default
\color inherit
/
\series bold
\shape italic
\color black
dbt
\series default
\shape default
\color inherit
=1).
 Prescaler distuiguishes two bit segments: TSEG1 (
\color red
Sync_Seg
\color inherit
 + 
\color red
Prop_Seg
\color inherit
 + 
\color red
Phase_Seg1
\color inherit
 parts of bit) and TSEG2 (
\color red
Phase_Seg2
\color inherit
 part of bit).
 Segment counter counts from 0, and it is restarted upon the end of previous
 segment or upon 
\color red
hard synchronisation
\color inherit
.
 Segment counter for 
\color red
nominal
\color inherit
(
\color red
data
\color inherit
) 
\color red
bit rate
\color inherit
 shall never overflow during 
\color red
nominal
\color inherit
(
\color red
data
\color inherit
) 
\color red
bit rate
\color inherit
.
 Segment counter for 
\color red
nominal bit rate
\color inherit
 may overflow during 
\color red
data bit rate
\color inherit
, and Segment counter for 
\color red
data bit rate
\color inherit
 may overflow during 
\color red
nominal bit rate
\color inherit
.
 Current 
\color red
bit rate 
\color inherit
is determined by Protocol control FSM based on CAN frame field being transmitted.
\end_layout

\begin_layout Standard
NBTCM is enabled always, apart from situations when CTU CAN FD is disabled.
 This is to make sure, that if error is detected during data bit rate (DBTCM
 is being used), NBTCM will be available for measuring duration of Ph2 ASAP
 after error was detected.
 DBTCM is enabled only during 
\color red
data bit rate
\color inherit
.
 During bits of CAN frame where 
\color red
bit rate
\color inherit
 is switched, both NBTCM and DBTCM are running.
 When NBTCM or DBTCM are disabled, none of its both counters are running
 (to save power).
 Both counters are erased when bit time segment ends to force alignment
 of 
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
 
\color red
time
\color inherit
 
\color red
quanta
\color inherit
 in the moment of 
\color red
bit rate
\color inherit
 switch.
\end_layout

\begin_layout Subsection
Bit segment meter
\end_layout

\begin_layout Description
File: bit_segment_meter.vhd
\end_layout

\begin_layout Standard
Bit segment meter module measures length of bit time segments (TSEG1 and
 TSEG2).
 Bit segment meter module maintains Expected segment length register (ESLR).
 ESLR contains number of 
\color red
time quanta
\color inherit
 that current bit segment shall last for.
 When current bit segment ends, ESLR is loaded with length of following
 bit segment.
 Loading of ESLR is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:segm-end-regular"
plural "false"
caps "false"
noprefix "false"

\end_inset

 for TSEG1 = 10 
\color red
time quanta
\color inherit
, TSEG2 = 5 
\color red
time quanta
\color inherit
 and BRP = 2.
 When 
\color red
positive resynchronisation
\color inherit
 occurs (see 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

), ESLR is increased (TSEG1 segment is lengthed) as in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:positive-resynchronisation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When 
\color red
negative resynchronisation
\color inherit
 occurs (see 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

), ESLR is decreased (TSEG2 is shortened).
 All rules for loading ESLR are described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:expected-segment-length"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="36line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="25line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Occurs when
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Loaded to value
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
End of segment TSEG1 due to 
\end_layout

\begin_layout Plain Layout
Segment counter equal to Expected segment length register - 1.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
PH2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Regular end of segment, no synchronisation.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
End of segment TSEG2 due to Segment counter equal to Expected segment length
 register - 1.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC + PROP + PH1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Regular end of segment, no synchronisation.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Positive resynchronisation
\color inherit
 with 
\color red
phase error
\color inherit
 <= SJW.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC + PROP + PH1 + Segment counter
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Segment counter = 
\color red
phase error
\color inherit
 in this case, therefore overall efect is as if TSEG1 was re-started with
 SYNC completed as in 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Positive resynchronisation
\color inherit
 with 
\color red
phase error
\color inherit
 > SJW.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC + PROP + PH1 + SJW
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Lengthening of TSEG1 by SJW.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Negative resynchronisation
\color inherit
 with 
\color red
phase error
\color inherit
 <= SJW.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC + PROP + PH1 - 1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Immediate end of segment.
 TSEG2 ends, therefore Expected segment length register is preloaded with
 length of TSEG1 - 1 (the same effect as hard synchronisation).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Negative resynchronisation
\color inherit
 with 
\color red
phase error =
\color inherit
 SJW + 1.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC + PROP + PH1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Immediate end of segment.
 TSEG2 ends since magnitude of phase error is equal to amount of SJW.
 Length of enxt segment is preloaded.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Negative resynchronisation
\color inherit
 with 
\color red
phase error
\color inherit
 > SJW.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
PH2 - SJW
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Shortening TSEG2 by SJW.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Hard synchronisation
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SYNC + PROP + PH1 - 1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TSEG1 length is subtracted by 1 since 
\color red
hard synchronisation
\color inherit
 shall restart Bit with SYNC segment completed according to 11.3.2.3 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Expected segment length register
\begin_inset CommandInset label
LatexCommand label
name "tab:expected-segment-length"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
When Segment counter is equal to, or higher than Expected segment length
 register - 1, Bit segment meter module issues End of segment request.
 End of segment request from Bit segment meter can be caused by:
\end_layout

\begin_layout Itemize
Segment counter equals Expected segment length - 1.
 Such a situation is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:segm-end-regular"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Itemize
Immediate end of segment occurs.
 See Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:immediate-segm-end"
plural "false"
caps "false"
noprefix "false"

\end_inset

 (SJW = 3).
\end_layout

\begin_layout Standard
Immediate end of segment is signalled when there is negative resynchronisation
 during TSEG2 and 
\color red
phase error
\color inherit
 <= SJW.
 Immediate resynchronisation causes Segment end request in the same clock
 cycle when 
\color red
resynchronisation
\color inherit
 edge occured.
 In this situation, TSEG2 segment ends immediately.
 This special case covers negative resynchronisation with BRP=1 and 
\color red
phase error
\color inherit
 <= SJW.
 The extra clock cycle needed to update Expected segment length register
 is undesirable, therefore immediate end of segment was introduced.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/segment_end_regular.pdf
	lyxscale 20
	scale 64

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Segment end - regular
\begin_inset CommandInset label
LatexCommand label
name "fig:segm-end-regular"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/positive_resynchronisation.pdf
	lyxscale 20
	scale 55

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Positive resynchronisation
\color inherit

\begin_inset CommandInset label
LatexCommand label
name "fig:positive-resynchronisation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/immediate_segm_end.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Immediate segment end
\begin_inset CommandInset label
LatexCommand label
name "fig:immediate-segm-end"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Segment end detector
\end_layout

\begin_layout Description
File: segment_end_detector.vhd
\end_layout

\begin_layout Standard
Segment end detector determines when segment ends based on requests as shown
 in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:segment-end-causes"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Segment end detector captures these requests and processes them when 
\color red
time quanta
\color inherit
 has elapsed (
\series bold
\shape italic
tq_edge
\color black
_nbt
\series default
\shape default
\color inherit
/
\series bold
\shape italic
\color black
dbt
\series default
\shape default
\color inherit
=1).
 If request arrives in the same clock cycle as 
\color red
time quanta
\color inherit
 has elapsed, it is processed immediately and not captured.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="36line%">
<column alignment="left" valignment="top" width="30line%">
<column alignment="left" valignment="top" width="25line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Request type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Issued by
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Segment end request (Nominal).
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit segment meter (Nominal)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Considered only during 
\color red
nominal bit rate
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Segment end request (Data).
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit segment meter (Data)
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Considered only during 
\color red
data bit rate
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Hard synchronisation
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synchronisation checker.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Considered only during 
\color red
nominal bit rate
\color inherit
.
 Shall not occur during 
\color red
data bit rate
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Segment end causes
\begin_inset CommandInset label
LatexCommand label
name "tab:segment-end-causes"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Bit rate switch
\end_layout

\begin_layout Standard
Since both Bit time counters (
\color red
nominal
\color inherit
 and 
\color red
data
\color inherit
) are running in bits where 
\color red
bit rate
\color inherit
 is switched (
\color red
BRS
\color inherit
 and 
\color red
CRC Delimiter
\color inherit
), length of TSEG2 of these bits is measured by both counters, and both
 Bit segment meter modules can provide Segment end request.
 Segment end detector only considers requests from 
\color red
resynchronisation
\color inherit
 module of actual bit rate as given by Protocol control FSM (
\series bold
sp_control
\series default
 signal).

\color red
 Bit rate
\color inherit
 switch is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:bit-rate-switch"
plural "false"
caps "false"
noprefix "false"

\end_inset

 (BRP nominal = 2, BRP data = 1, TSEG1 nominal = 10, TSEG1 data = 7, TSEG2
 data = 6).
 Note that in this Figure Time quanta counter, Time quanta edge, Segment
 counter and Expected segment length register are different signals for
 
\color red
nominal
\color inherit
 / 
\color red
data
\color inherit
 
\color red
bit rate
\color inherit
 but 
\begin_inset Quotes eld
\end_inset

Nominal
\begin_inset Quotes erd
\end_inset

 version are shown in 
\color red
nominal bit rate
\color inherit
 and 
\begin_inset Quotes eld
\end_inset

Data
\begin_inset Quotes erd
\end_inset

 versions are shown in 
\color red
data bit rate
\color inherit
.
\end_layout

\begin_layout Standard
Note that in the moment of 
\color red
bit rate
\color inherit
 switch, Protocol control FSM provides actualized 
\series bold
sp_control
\series default
 (bit rate) already in Process pipeline stage.
 Sample control is driven by DFF which is bypassed in this moment so that
 first 
\color red
time quanta 
\color inherit
of TSEG2 after 
\color red
bit rate
\color inherit
 switch is measured with proper 
\color red
bit rate
\color inherit
 selected!
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/bit_rate_switch.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Bit rate
\color inherit
 switch
\begin_inset CommandInset label
LatexCommand label
name "fig:bit-rate-switch"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Prescaler FSM
\end_layout

\begin_layout Description
File: bit_time_fsm.vhd
\end_layout

\begin_layout Standard
Prescaler FSM determines actual bit time segment (TSEG1, TSEG2).
 Its state transition diagram is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:fsm-prescaler"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Prescaler FSM issues requests to generate TX trigger and RX triggers to
 Trigger generator.
 TX trigger is requested upon the end of TSEG2 segment (start of new bit,
 bit value is transmitted).
 RX trigger is requested upon the end of TSEG1 segment (
\color red
sample point
\color inherit
, bit value is sampled).
\end_layout

\begin_layout Standard
\begin_inset Float figure
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/FSM_prescaler.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Prescaler FSM
\begin_inset CommandInset label
LatexCommand label
name "fig:fsm-prescaler"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Trigger generator
\begin_inset CommandInset label
LatexCommand label
name "subsec:Trigger-generator"

\end_inset


\end_layout

\begin_layout Description
File: trigger_generator.vhd
\end_layout

\begin_layout Standard
Trigger generator processes requests to generate TX trigger (used to process
 data in Stuff pipeline stage), and RX triggers (used to process data in
 Destuff and Process pipeline stages).
 Typical scenario is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:tx-rx-triggers"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 As there is no lower limit on length of TSEG2 from 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

, resynchronisation which shortens length of TSEG2 to just one clock cycle
 can occur (assuming BRP=1).
 In such case, RX trigger for Process pipeline stage and TX trigger for
 Stuff pipeline stage would overlap.
 This is not acceptable since Stuff pipeline stage needs Process pipeline
 stage to be finished before it can proceed (new transmitted data must be
 provided by Protocol control FSM before being 
\begin_inset Quotes eld
\end_inset

stuffed
\begin_inset Quotes erd
\end_inset

).
 To avoid this situation, TX trigger is shifted by one clock cycle as is
 shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:tx-trigger-shift"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Stuff pipeline stage is also shifted by one clock cycle (from last clock
 cycle of TSEG2 to first clock cycle of TSEG1).
 As value of 
\color red
information processing time
\color inherit
 of CTU CAN FD is 2, this situation corresponds to shortening length of
 TSEG2 to less than information processing time.
 Shifting of TX trigger corresponds to delaying calculation of following
 bit value after 
\color red
information processing time
\color inherit
 from 
\color red
sample point
\color inherit
 as defined in 11.3.2.4 of 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/prescaler_triggers.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TX, RX triggers
\begin_inset CommandInset label
LatexCommand label
name "fig:tx-rx-triggers"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/prescaler_triggers_throttling.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TX trigger shift
\begin_inset CommandInset label
LatexCommand label
name "fig:tx-trigger-shift"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Synchronisation control
\end_layout

\begin_layout Standard
Type of 
\color red
synchronisation
\color inherit
 is controlled by Protocol control FSM based on current part of CAN frame
 as is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:synchronisation-control"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="25line%">
<column alignment="left" valignment="top" width="50line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Synchronisation type
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used during Protocol control FSM state
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Hard synchronisation
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Suspend transmission
\color inherit
, 2nd or 3rd bit of 
\color red
intermission
\color inherit
, 
\color red
bus idle
\color inherit
, 
\color red
integration
\color inherit
, 
\color red
reintegration
\color inherit
, 
\color red
FDF
\color inherit
/
\color red
res
\color inherit
 bit edge in CAN FD Frame.
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TSEG1 is started with SYNC segment complement.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No 
\color red
synchronisation
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
All other parts
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\color inherit
 operating in 
\color red
data bit rate
\color inherit
 does not synchronise.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No 
\color red
synchronisation
\color inherit
 for 
\color red
phase error
\color inherit
 > 0
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
All other parts
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Node sending 
\color red
dominant
\color inherit
 bit does not perform 
\color red
resynchronisation
\color inherit
 or 
\color red
hard synchronisation
\color inherit
 as a result of 
\color red
positive phase error
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Resynchronisation
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
All other parts
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
All other 
\color red
recessive
\color inherit
 to 
\color red
dominant
\color inherit
 edges are used for 
\color red
resynchronisation
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Synchronisation control
\begin_inset CommandInset label
LatexCommand label
name "tab:synchronisation-control"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Synchronisation checker
\end_layout

\begin_layout Description
File: synchronisation_checker.vhd
\end_layout

\begin_layout Standard
Synchronisation checker determines if 
\color red
synchronisation
\color inherit
 edge (detected by Bus sampling, see 
\begin_inset CommandInset ref
LatexCommand ref
reference "sec:Bus-sampling"
plural "false"
caps "false"
noprefix "false"

\end_inset

) is valid for synchronisation accroding to 11.3.2.1 
\begin_inset CommandInset citation
LatexCommand cite
key "key-1"
literal "false"

\end_inset

.
 Synchronisation checker maintains Synchronisation edge flag.
 This flag is set when 
\color red
synchronisation
\color inherit
 edge occurs, and cleared when TSEG1 ends (
\color red
sample point
\color inherit
 of bit).
 If this flag is set, and another 
\color red
synchronisation
\color inherit
 edge occurs before the flag is cleared, such edge is ignored.
 Therefore, if there is more than one synchronisation edge between two consecuti
ve 
\color red
sample points
\color inherit
, only first edge is detected as valid edge and other edges are ignored.
 A situation where two 
\color red
synchronisation
\color inherit
 edges are detected (and second one is filtered out) is shown in Figure
 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:prescaler-sync-edge-validation."
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When 
\color red
synchronisation
\color inherit
 edge is valid for 
\color red
synchronisation
\color inherit
, it causes 
\color red
resynchronisation
\color inherit
, 
\color red
hard synchronisation
\color inherit
 or no 
\color red
synchronisation
\color inherit
 according to rules in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:synchronisation-control"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/prescaler_synchronisation_validation.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Synchronisation edge filtration
\begin_inset CommandInset label
LatexCommand label
name "fig:prescaler-sync-edge-validation."

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Section
Bus sampling
\begin_inset CommandInset label
LatexCommand label
name "sec:Bus-sampling"

\end_inset


\end_layout

\begin_layout Description
File: bus_sampling.vhd
\end_layout

\begin_layout Standard
Bus sampling module implements following functionality:
\end_layout

\begin_layout Itemize
Synchronizes 
\series bold
can_rx
\series default
 input to System clock domain.
\end_layout

\begin_layout Itemize
Samples bus in 
\color red
sample point 
\color inherit
(Destuff pipeline stage).
\end_layout

\begin_layout Itemize
Detects edges on sampled 
\series bold
can_rx
\series default
 and 
\series bold
can_tx
\series default
.
 Detect 
\color red
synchronisation
\color inherit
 edges.
\end_layout

\begin_layout Itemize
Measures 
\color red
transmitter delay
\color inherit
 and calculate 
\color red
secondary sample point
\color inherit
 offset.
\end_layout

\begin_layout Itemize
Creates 
\color red
secondary sample point
\color inherit
 (SSP).
\end_layout

\begin_layout Itemize
Detects 
\color red
bit error
\color inherit
.
\end_layout

\begin_layout Standard
Block diagram of Bus sampling is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:bus-sampling"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_Bus_sampling.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Bus sampling block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:bus-sampling"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Bus sampling implements 2 DFF synchronizer to synchronize asynchronous 
\series bold
can_rx
\series default
 input.
 Output of this synchronizer is sampled in 
\color red
sample point
\color inherit
, and stored to Previous bus value register.
 Output of this synchronizer is also connected as data input to Bit destuffing
 module, therefore bus is sampled in the same moment as input serial data
 from CAN bus are processed by Bit destuffing.
 This synchronizer is clocked with System clock, and it is always enabled.
 
\end_layout

\begin_layout Standard
Bus sampling detects edges on 
\series bold
can_rx
\series default
 and 
\series bold
can_tx
\series default
.
 
\color black
Edges on 
\series bold
can_tx
\series default
 are detected with granularity of System clock period.
 Edges on 
\series bold
can_rx
\series default
 are detected with granularity of 
\color red
time quanta 
\color black
(Edges are gated by Time quanta edge provided by Prescaler).
 
\color inherit
Only 
\color red
recessive
\color inherit
 to 
\color red
dominant
\color inherit
 edges are detected on 
\series bold
can_rx
\series default
.
 Furthermore, edge on 
\series bold
can_rx
\series default
 is detected only when bus value (synchronizer output) has opposite value
 than bus value sampled in previous 
\color red
sample point
\color inherit
 (Therefore previous sampled bus value must be 
\color red
recessive
\color inherit
).
 Detected edge on 
\series bold
can_rx
\series default
 is propagated as 
\color red
synchronization
\color inherit
 edge to Prescaler.
 Edge on 
\series bold
can_tx
\series default
 is detected regardless of previous sampled bus value, but only 
\color red
recessive
\color inherit
 to 
\color red
dominant
\color inherit
 edges are detected.
 A typical scenario of edge detection on 
\series bold
can_tx/can_rx
\series default
 is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:edge-detection"
plural "false"
caps "false"
noprefix "false"

\end_inset

 (with BRP=2).
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/edge_detection_rx.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Edge detection
\begin_inset CommandInset label
LatexCommand label
name "fig:edge-detection"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Transmitter delay measurement
\end_layout

\begin_layout Description
File: trv_delay_meas.vhd
\end_layout

\begin_layout Standard

\color red
Transmitter delay
\color inherit
 is a roundtrip delay from 
\series bold
can_tx
\series default
 to 
\series bold
can_rx
\series default
 upon transmission of 
\color red
dominant
\color inherit
 bit.
 This delay includes propagation of signal to physical layer transceiver,
 delay of transceiver and propagation of signal back.
 
\color red
Transmitter delay
\color inherit
 is measured in CAN FD frames between falling edge of 
\color red
FDF
\color inherit
 (
\color red
EDL
\color inherit
) bit, and following r0 bit.
 In CAN 2.0 frames, 
\color red
Transmitter delay
\color inherit
 is not measured.
 
\color red
Transmitter delay
\color inherit
 is measured in multiples of System clock (not 
\color red
time quanta
\color inherit
) and its measurement is controlled by Protocol control FSM.
 Measurement is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:transceiver-delay-measurement"
plural "false"
caps "false"
noprefix "false"

\end_inset

 and shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:transceiver-delay-measurement"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
Measured 
\color red
transmitter delay
\color inherit
 can be read out from TRV_DELAY register via SW.
 Transmitter delay readable from TRV_DELAY register is shadowed, and the
 shadowed value is changed upon the end of 
\color red
transmitter delay
\color inherit
 measurement.
 Therefore if SW reads TRV_DELAY during measurement, it will read previous
 measured value.
 New value will be read only after the end of current measurement.
 To read proper value of 
\color red
transmitter delay
\color inherit
 from TRV_DELAY, at least one CAN FD frame must have been transmitted since
 previous reset, otherwise 0 will be read from TRV_DELAY register.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="8" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Transmitter
\color inherit
 of CAN FD frame reaches 
\color red
sample point
\color inherit
 of 
\color red
FDF
\color inherit
 (
\color red
EDL
\color inherit
) bit.
 It enables measurement of 
\color red
transmitter delay
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
At start of next bit (Stuff pipeline stage, r0 bit), Protocol control transmits
 
\color red
dominant
\color inherit
 bit.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
An edge on 
\series bold
can_tx
\series default
 is detected by Bus sampling.
 Transmitter delay counter is erased.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transmitter delay counter is incremented by 1 each clock cycle.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
The 
\color red
dominant
\color inherit
 value which was transmitted in Step 2, propagates to physical layer transceiver
 and back to 
\series bold
can_tx
\series default
 input of CTU CAN FD.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
can_rx
\series default
 input is synchronized by 2 DFF synchronizer to System clock domain.
 Delay of synchronizer is included in measured 
\color red
transmitter delay
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus sampling detects edge on 
\series bold
can_rx
\series default
.
 Measurement is finished, new value can bea read from TRV_DELAY register.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Transmitter delay
\color inherit
 measurement
\begin_inset CommandInset label
LatexCommand label
name "tab:transceiver-delay-measurement"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/transceiver_delay_measurement.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Transmitter delay
\color inherit
 measurement
\begin_inset CommandInset label
LatexCommand label
name "fig:transceiver-delay-measurement"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Secondary sampling point offset
\end_layout

\begin_layout Standard

\color red
Secondary sampling point
\color inherit
 offset is calculated as offset from start of bit (
\color red
SyncSeg
\color inherit
 field) in multiples of System clock.
 
\color red
Secondary sampling point
\color inherit
 offset can be configured by SW from SSP_CFG register according to Table
 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ssp-config"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 
\color red
Secondary sampling point
\color inherit
 offset can have values between 0 and 127.
 If 
\color red
secondary sampling point
\color inherit
 offset is 0, 
\color red
secondary sampling point
\color inherit
 is active in the same clock cycle as TX trigger.
 If 
\color red
secondary sampling point
\color inherit
 offset is higher than 127 (e.g.
 measured 
\color red
transmitter delay
\color inherit
 + offset > 127), it is saturated to 127.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="20line%">
<column alignment="left" valignment="top" width="73.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Configuraton name
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Offset
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Position of 
\color red
secondary sampling point
\color inherit
 is fixed at SSP_CFG[SSP_OFFSET].
 Measured 
\color red
transmitter
\color inherit
 
\color red
delay
\color inherit
 is not taken into account.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Offset + 
\color red
transmitter delay
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Position of 
\color red
secondary sampling point
\color inherit
 is given as SSP_CFG[SSP_OFFSET] + Measured 
\color red
transmitter delay
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No SSP
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Bit rate
\color inherit
 within Prescaler is never changed to 
\begin_inset Quotes eld
\end_inset

Secondary
\begin_inset Quotes erd
\end_inset

, it only changes to 
\begin_inset Quotes eld
\end_inset

Data
\begin_inset Quotes erd
\end_inset

 even for transmitter of CAN FD frame, and bus is sampled at moment of 
\color red
data bit rate sample point
\color inherit
.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Secondary sampling point
\color inherit
 configuration
\begin_inset CommandInset label
LatexCommand label
name "tab:ssp-config"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Secondary sampling point generator
\end_layout

\begin_layout Description
File: ssp_generator.vhd
\end_layout

\begin_layout Standard

\color red
Secondary sampling point
\color inherit
 (SSP) is created by delaying TX trigger by the amount of 
\color red
SSP
\color inherit
 offset as is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:secondary-sampling-point"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 When bit rate is switched from Nominal to Data, first 
\color red
SSP
\color inherit
 is delayed from TX trigger by the amount of 
\color red
SSP
\color inherit
 offset.
 As 
\color red
SSP 
\color inherit
is used to detect bit errors by Transmitters of CAN FD frames during data
 bit rate, each next 
\color red
SSP
\color inherit
 is located whole data bit time later from previous 
\color red
SSP
\color inherit
 (there is no resynchronisation by Transmitters in data bit rate, so bit
 time is not shortened, nor lengthened).
 The position of first three 
\color red
SSPs 
\color inherit
is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:secondary-sampling-point-positions"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 The relationship between first 
\color red
SSPs
\color inherit
 and next 
\color red
SSPs
\color inherit
 is used by SSP generator module which creates SSP, and provides it to Bit
 error detector.
 Operation of SSP generator is described in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ssp-generator-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/ssp_offset.pdf
	lyxscale 20
	scale 63

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Secondary sampling point
\color inherit

\begin_inset CommandInset label
LatexCommand label
name "fig:secondary-sampling-point"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/SSP_timing.pdf
	lyxscale 20

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Secondary sampling point
\color inherit
 positions
\begin_inset CommandInset label
LatexCommand label
name "fig:secondary-sampling-point-positions"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="8" columns="2">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="5line%">
<column alignment="left" valignment="top" width="88.5line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Action
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CTU CAN FD is transmitter of CAN FD frame where bit rate will be switched.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control switched bit rate in sample point of BRS bit.
 Protocol control configures SSP generator to measure length of data bit
 time and to create first SSP.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SSP generator waits for first TX trigger in data bit rate and starts measurement
 of data bit time length when TX trigger is active (by means of so called
 SSP counter (SSPC)).
 SSP generator starts measuring delay of SSP offset from TX trigger (by
 means of so called Bit time measurement counter (BTMC)).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When next TX trigger occurs (at start of next bit), SSP generator stops
 measurement of data bit time in SSPC.
 Now SSP generator knows distance between each next SSP (SSPC value).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
5
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
When BTMC reaches value of SSP offset, SSP generator creates first SSP.
 
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
6
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
SSPC is restarted, and position of next sample point starts to be calculated
 by SSPC.
 Now the delay of each next SSP is given by data bit time length (value
 of BTMC).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
7
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Step 5 is repeated for each SSP until the end of data phase of CAN FD frame.
 Note that SSPC can reach value of SSP offset for first SSP sooner than
 BTMC measurement will finish (This position occurs when SSP position is
 located within the same bit time).
 This does not mind, since value of BTMC will always be higher than SSPC,
 therefore SSPC can count when BTMC is still running.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
SSP
\color inherit
 generator operation
\begin_inset CommandInset label
LatexCommand label
name "tab:ssp-generator-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Bit error detection
\end_layout

\begin_layout Description
File: bit_err_detector.vhd
\end_layout

\begin_layout Standard

\color red
Bit error
\color inherit
 detection differs for 
\color red
nominal
\color inherit
 
\color red
bit rate
\color inherit
, 
\color red
data bit rate
\color inherit
 and 
\color red
Secondary sampling
\color inherit
 as is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:bit-error-detection"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Note that 
\color red
bit error
\color inherit
 is detected by Bus sampling always when CTU CAN FD is enabled (SETTINGS[ENA]
 = 1).
 
\color red
Bit error
\color inherit
 is only ignored by Error detector module when it is irrelevant as shown
 in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:Bit-error-exceptions"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 
\color red
Bit error
\color inherit
 detection in 
\color red
nominal
\color inherit
 
\color red
bit rate
\color inherit
 is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:bit-error-detection"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="4" columns="3">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="60line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit-Rate
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Detected when
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Nominal bit rate
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX trigger 1 is active
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Detected when 
\series bold
can_tx
\series default
 value (transmitted value of actual bit) is not equal to
\series bold
can_rx
\series default
 value (sampled bus value).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Data bit rate
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX trigger 1 is active
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Detected when 
\series bold
can_tx
\series default
 value (transmitted value of actual bit) is not equal to 
\series bold
can_rx
\series default
 value (sampled bus value).
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Secondary sample
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\color red
Secondary sample point
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Detected when 
\series bold
can_tx
\series default
 value on the output of TX data cache is not equal to 
\series bold
can_rx
\series default
 value (sampled bus value).
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
Bit Error detectiron
\begin_inset CommandInset label
LatexCommand label
name "tab:bit-error-detection"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/bit_error_detection.pdf
	lyxscale 20
	scale 60

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout

\color red
Bit error
\color inherit
 detection
\begin_inset CommandInset label
LatexCommand label
name "fig:bit-error-detection"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
TX data cache
\end_layout

\begin_layout Description
File: tx_data_cache.vhd
\end_layout

\begin_layout Standard
To detect 
\color red
bit error
\color inherit
 in Secondary sampling, CTU CAN FD needs to remember 
\series bold
can_tx
\series default
 values of several bits transmitted on CAN bus (
\color red
secondary sample point
\color inherit
 can be so late, that it does not fit within the bit itself, and may occurs
 in following bits, therefore, a transmitted bit value must be rememebered
 until 
\color red
secondary sample point
\color inherit
).
 This functionality is implemented by TX data cache.
 TX data cache is a FIFO memory with each entry containing a single bit.
 
\series bold
can_tx
\series default
 value is stored to TX data cache directly after a bit was transmitted to
 the bus (SYNC segment, One clock cycle after Stuff pipeline stage).
 TX data cache can store up to 8 bit values (therefore allowing 8 bits on
 the fly).
 A value is read from TX data cache when 
\color red
secondary sampling point
\color inherit
 is active.
 TX data cache operation together with 
\color red
bit error
\color inherit
 detection during Secondary Sampling is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:tx-data-cache-operation"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Timing_diagrams/PDFs/bit_error_ssp.pdf
	lyxscale 20
	scale 44

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
TX data cache operation
\begin_inset CommandInset label
LatexCommand label
name "fig:tx-data-cache-operation"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Section
Memory registers
\end_layout

\begin_layout Description
File: memory_registers.vhd
\end_layout

\begin_layout Standard
Memory registers implement following functionality:
\end_layout

\begin_layout Itemize
Contains configuration and status registers of CTU CAN FD (accessed by SW).
\end_layout

\begin_layout Itemize
Issues commands to CTU CAN FD by SW.
\end_layout

\begin_layout Itemize
Reads received CAN frame from RX buffer RAM.
\end_layout

\begin_layout Itemize
Writes CAN frame to be transmitted to TXT buffer RAMs.
\end_layout

\begin_layout Standard
Block diagram of Memory registers is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:memory-registers-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/BD_memory_registers.pdf
	lyxscale 20
	scale 80

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Memory registers block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:memory-registers-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Memory registers contain Control registers and Test registers modules which
 are generated by 
\begin_inset CommandInset citation
LatexCommand cite
key "key-7"
literal "false"

\end_inset

.
 Control registers, Test Registers and format of CAN frame as is stored
 in TXT buffers and RX buffer are described in IP-XACT format with slight
 modifications as explained in 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ip-xact-attributes"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Memory map is edited via Kactus2 tool.
 Test registers module is present only when 
\series bold
\shape italic
sup_test_regsiters=true
\series default
\shape default
.
\end_layout

\begin_layout Standard
From one side, Control registers and Test Registers modules are accessed
 via simple RAM-like memory interface which is described in 
\begin_inset CommandInset ref
LatexCommand ref
reference "subsec:RAM-like-interface"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 From other side, Control registers and Test Registers modules are accessible
 via two records: Output record (signals going from registers modules to
 rest of CTU CAN FD) and Input record (signals going from rest of CTU CAN
 FD to registers modules).
\end_layout

\begin_layout Standard
Memory registers block decodes write accesses to TXT buffers (via TXT buffer
 1 to TXT buffer 8 memory locations) and maps these accesses to access TXT
 buffer RAMs.
\end_layout

\begin_layout Subsection
Register types
\end_layout

\begin_layout Standard
Control registers module contains following types of registers:
\end_layout

\begin_layout Subsubsection
Read/Write register
\end_layout

\begin_layout Standard
A DFF is instantiated and connected to output record (write value).
 When register is read, value in this DFF is returned.
\end_layout

\begin_layout Subsubsection
Read only register
\end_layout

\begin_layout Standard
No DFF is instantiated.
 When register is read, value from Input record is returned.
\end_layout

\begin_layout Subsubsection
Write only register
\end_layout

\begin_layout Standard
A DFF is instantiated and connected to output record (write value).
 When register is read, all zeroes are returned.
\end_layout

\begin_layout Subsubsection
Read/Write Once register
\end_layout

\begin_layout Standard
A DFF is instantiated and connected to output record (write value).
 When register is read, value from Input record is used.
 This type of register is used when write value has different meaning than
 read value.
\end_layout

\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset


\end_layout

\begin_layout Subsection
Register attributes
\begin_inset CommandInset label
LatexCommand label
name "subsec:Register-attributes"

\end_inset


\end_layout

\begin_layout Standard
Registers within Control registers module use additional IP-XACT attributes
 as is shown in Table 
\begin_inset CommandInset ref
LatexCommand ref
reference "tab:ip-xact-attributes"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement h
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="5" columns="5">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="10line%">
<column alignment="left" valignment="top" width="15line%">
<column alignment="left" valignment="top" width="40line%">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
IP XACT attribute
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Attribute value
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Applied on
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Used on registers
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
cellcolor{gray}
\end_layout

\end_inset


\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Modified write value
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
clear
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Register field
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
COMMAND, MODE[RST], INT_STAT,
\end_layout

\begin_layout Plain Layout
INT_ENA_CLR,
\end_layout

\begin_layout Plain Layout
INT_ENA_SET,
\end_layout

\begin_layout Plain Layout
INT_MASK_CLR,
\end_layout

\begin_layout Plain Layout
INT_MASK_SET,
\end_layout

\begin_layout Plain Layout
TX_COMMAND,
\end_layout

\begin_layout Plain Layout
CTR_PRES
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
No DFF is instantiated in the register, but written value is only combinatoriall
y decoded and connected to Output record.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Is present
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
IP_XACT parameter name
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Register
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
FILTER_*_MASK,
\end_layout

\begin_layout Plain Layout
FILTER_*_VAL
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Register is instantiated only when VHDL generic with the same name as IP-XACT
 parameter is set to 
\begin_inset Quotes eld
\end_inset

true
\begin_inset Quotes erd
\end_inset

.
 When generic is 
\begin_inset Quotes eld
\end_inset

false
\begin_inset Quotes erd
\end_inset

, register is not instantiated and its reset value is returned upon read
 (if it is readable).
 Value of this generic is added to generics of Control registers module.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read action
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
modify
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Register field
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX_DATA
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Read signaller module is instantiated.
 This module combinatorially decodes when register field is being read and
 provides this information in Output record.
 Used to signal to RX buffer that there is a read from RX_DATA register.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Vendor extension - regLocks/ regLock
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
name= register name
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Register
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
EWL/ ERP/ CTR_PRES
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
If specified, register is writable only when 
\series bold
\shape italic
lock
\series default
\shape default
 = 0.
 If not specified, 
\series bold
\shape italic
lock
\series default
\shape default
 input has no effect.
 This is used to prevent user from writing EWL/ERP/CTR_PRES unless CTU CAN
 FD is in test mode.
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Caption Standard

\begin_layout Plain Layout
IP-XACT register attributes
\begin_inset CommandInset label
LatexCommand label
name "tab:ip-xact-attributes"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-1"

\end_inset

ISO11898-1 2015 - Road vehicles, Controller area network, Part 1, Data link
 layer and signalling
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-2"

\end_inset

CTU CAN FD - Datasheet
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-3"

\end_inset

Avalon@ Interface specification, 2018-09-26, Intel
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-4"

\end_inset

AMBA 3 APB Protocol, v1.0, Specification, ARM
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-5"

\end_inset

AMBA 3 AHB-Lite Protocol, v1.0, Specification, ARM
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-6"

\end_inset

CAN with Flexible Data-Rate, Specification, Version 1.0, April 2012, BOSCH
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-7"

\end_inset

Register map generation tool, 
\begin_inset Flex URL
status open

\begin_layout Plain Layout

https://github.com/Blebowski/Reg_Map_Gen
\end_layout

\end_inset


\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-5"

\end_inset

CTU CAN FD - Testbench architecture
\end_layout

\end_body
\end_document
