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\pdf_author "Ille Ondrej"
\pdf_subject "CAN FD IP function"
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\begin_layout Title

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CTU CAN
\noun on
 FD 
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IP CORE
\noun default
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Datasheet
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Czech Technical University in Prague
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Faculty of Electrical Engineering
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Department of Measurement
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CTU CAN FD IP Core - Testbench
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Version 2.1.5
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Document Version
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Author
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Date
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0.1
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Ondrej Ille
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01-2020
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Initial version after separation of TB document from System architecture.
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mainmatter
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\begin_layout Chapter*
Format
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addcontentsline{toc}{chapter}{Format}
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\begin_layout Standard
Throughout this data sheet following notations are kept:
\end_layout

\begin_layout Itemize
Common text is written with this font.
\end_layout

\begin_layout Itemize
Memory registers are always described with capital letters e.g.
 REGISTER or REGISTER [BIT_FIELD] to represent register or bit field within
 a register.
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\begin_layout Chapter
Introduction
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thispagestyle{fancy}
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\begin_layout Standard
This document describes testbenches and test architecture for CTU CAN FD.
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\begin_layout Section
Dependencies
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\begin_layout Standard
To run tests of CTU CAN FD, following dependencies are needed:
\end_layout

\begin_layout Itemize
GTKWave - Waveform viewer.
\end_layout

\begin_layout Itemize
VUnit - Unit test framework for VHDL.
 Custom modifications are done to allow interactive graphic debugging (
\begin_inset Flex URL
status open

\begin_layout Plain Layout

https://github.com/mjerabek/vunit
\end_layout

\end_inset

).
\end_layout

\begin_layout Itemize
GHDL - VHDL simulator.
 Custom modifications are done to speed-up dumping of waveforms to GHW file
 (
\begin_inset Flex URL
status open

\begin_layout Plain Layout

https://github.com/Blebowski/ghdl
\end_layout

\end_inset

).
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\begin_layout Itemize
Python 3 - To run VUnit.
 Following Python modules are used: pyvcd attrs jinja2 parsy pyyaml click
 yattag json2html
\end_layout

\begin_layout Standard
There is a docker Image available which is ready to run the simulations
 available at: 
\begin_inset Flex URL
status open

\begin_layout Plain Layout

https://gitlab.com/canfd/server-tools/container_registry
\end_layout

\end_inset

.
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\begin_layout Section
How to run test environment?
\end_layout

\begin_layout Standard
Test environment can be started (from docker image) in root directory of
 the project as:
\end_layout

\begin_layout Quotation

\series bold
./run-docker-test
\end_layout

\begin_layout Section
How to run tests?
\end_layout

\begin_layout Standard
Tests (regression) can be started by 
\begin_inset Quotes eld
\end_inset

run
\begin_inset Quotes erd
\end_inset

 script like so:
\end_layout

\begin_layout Quotation

\series bold
run.py test <config_file>
\end_layout

\begin_layout Standard
Where <config_file> describes test configuration (see TODO).
 There are two main configuration sets: Fast (must pass before merge) and
 Nightly (should be debugged before release).
 These can be run like so:
\end_layout

\begin_layout Quotation

\series bold
run.py test tests_fast.yml
\end_layout

\begin_layout Quotation

\series bold
run.py test tests_nightly.yml
\end_layout

\begin_layout Standard
Note that these commands will run given configuration in single thread only.
 Gitlab CI is using parallel run (to save time), where up to N instances
 can be ran in parallel (N being number of cores in a system).
 In such a case, tests can be run from Makefile:
\end_layout

\begin_layout Quotation

\series bold
make tests_fast
\end_layout

\begin_layout Quotation

\series bold
make tests_nightly
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\begin_layout Standard
To extract coverage (so far from GHDL via GCov, which is not real HW coverage,
 but at least something):
\end_layout

\begin_layout Quotation

\series bold
make coverage
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\begin_layout Standard
To extract PSL functional coverage after tests has been executed:
\end_layout

\begin_layout Quotation

\series bold
make functional_coverage
\end_layout

\begin_layout Standard
To debug interactively with GTKWave:
\end_layout

\begin_layout Quotation

\series bold
run.py test tests_fast.yml -- -g
\end_layout

\begin_layout Standard
VUnit supports multiple simulators to be used and in history this project
 used also Modelsim.
 Right now support for Modelsim is non-functional since free version of
 Modelsim does not support PSL assertions.
 However, if e.g.
 Modelsim DE is used, user can switch to it from GHDL for test run like
 so:
\end_layout

\begin_layout Quotation

\series bold
VUNIT_SIMULATOR=modelsim ./run.py test tests_fast.yml
\end_layout

\begin_layout Section
Wave dumping
\end_layout

\begin_layout Standard
By default when debugging interactively, all signal waves are dumped to
 GHW file.
 This can take significant amount of time in case of bit test cases (typically
 sanity tests).
 To speed this up, only sub-set of waves can be dumped to GHW file.
 To do this, Modelsim wave files need to be first converted to Wave opt
 files for GHDL.
 This is further described in TODO.
 This can be executed like so:
\end_layout

\begin_layout Quotation

\series bold
run.py test tests_fast.yml --create-ghws
\end_layout

\begin_layout Standard
Which will elaborate the design and generate wave files for most needed
 signals for debugging.
 Consecutive run with 
\begin_inset Quotes eld
\end_inset

-g
\begin_inset Quotes erd
\end_inset

 option will then start GTKWave with layout file already loaded.
 
\end_layout

\begin_layout Section
Test configuration
\end_layout

\begin_layout Standard
Configuration of regression runs is in YAML config files: 
\series bold
tests_fast.yml
\series default
 and 
\series bold
tests_nightly.yml
\series default
.
 Meaning of entries within config files is following:
\end_layout

\begin_layout Description
log_level Severity of log messages which will be printed to log file during
 test run.
 Available options are: info, debug, warning and error.
\end_layout

\begin_layout Description
psl_coverage Whether PSL coverage / assertions will be collected.
 This option is supported only for GDHL.
\end_layout

\begin_layout Description
error_tolerance Number of errors which are tolerated before test fails.
 This option is deprecated.
 Tests fails ALWAYS when there is any log with severities Error or Failure.
\end_layout

\begin_layout Description
randomize Whether test run should be randomized.
 Available options: True / False.
\end_layout

\begin_layout Description
seed If test is not randomized, this seed will be used.
 If not specfied, seed=0 will be used.
\end_layout

\begin_layout Description
dump_all_signals When GHW Wave opt file is present, it will be ignored and
 all signals will be dumped to GHW file.
\end_layout

\begin_layout Description
timeout Simulation timeout (from simulation time perspective).
\end_layout

\begin_layout Description
iterations Number of iterations each test should execute in single run.
\end_layout

\begin_layout Description
wave Path to Modelsim Wave file.
\end_layout

\begin_layout Section
Test types
\end_layout

\begin_layout Standard
There are 4 possible test types in CTU CAN FD verification:
\end_layout

\begin_layout Description
Unit Test each unit towards its expected functionality.
\end_layout

\begin_layout Description
Feature Test functionality of CTU CAN FD as whole in specific situations.
\end_layout

\begin_layout Description
Sanity Test implements various bus topologies and simulates bus traffic
 with more controllers.
\end_layout

\begin_layout Description
Reference Test verifies communication with existing CAN FD implementation.
\end_layout

\begin_layout Section
Test evaluation
\end_layout

\begin_layout Standard
All tests are architected with 
\begin_inset Quotes eld
\end_inset

fail fast
\begin_inset Quotes erd
\end_inset

 approach, therefore errors are not tolerated.
 Each log with 
\begin_inset Quotes eld
\end_inset

error
\begin_inset Quotes erd
\end_inset

 or 
\begin_inset Quotes eld
\end_inset

failure
\begin_inset Quotes erd
\end_inset

 severity immediately causes test to fail.
\end_layout

\begin_layout Chapter
Unit tests
\end_layout

\begin_layout Standard
Each unit test tests functionality of a single module within CTU CAN FD.
 There are no test-cases in unit tests each unit test has several 
\begin_inset Quotes eld
\end_inset

driving
\begin_inset Quotes erd
\end_inset

 processes and 
\begin_inset Quotes eld
\end_inset

monitoring
\begin_inset Quotes erd
\end_inset

 processes.
 Each unit test has a process which controls execution of a test.
\end_layout

\begin_layout Section
CRC unit test
\end_layout

\begin_layout Standard
CRC unit test generates random bit sequence 10 to 620 bits long (
\family roman
\shape italic
gen_bit_sequence
\family default
\shape default
) and random 
\family roman
\shape italic
drv_fd_type
\family default
\shape default
 setting.
 According to TODOISO standard, there is different initialization vector
 in CRC shift register in ISO CAN FD protocol as in non-ISO CAN protocol.
 Signal 
\family roman
\shape italic
drv_fd_type
\family default
\shape default
 distinguishes between these two options.
 Then CRC is calculated in software (model) by 
\family roman
\shape italic
calc_crc
\family default
\shape default
 procedure.
 Afterwards, generated bit sequence is applied to DUT input.
 Triggering signals are generated by 
\family roman
\shape italic
sample_gen
\family default
\shape default
 process, and serial data are processed by CRC circuit.
 At the end, software calculated CRC and DUT output are compared.
 If these two are not equal, an error is detected.
\end_layout

\begin_layout Section
Bit stuffing and Bit destuffing
\end_layout

\begin_layout Standard
This unit test tests 
\begin_inset Quotes eld
\end_inset

Bit Stuffing
\begin_inset Quotes erd
\end_inset

 and 
\begin_inset Quotes eld
\end_inset

Bit De-stuffing
\begin_inset Quotes erd
\end_inset

 module as well.
 Architecture of this testbench is shown in Figure TODO.
 Both circuits are connected in a chain, after bit stuffing serial data
 stream is fed to bit destuffing.
 In each step of unit test, following random inputs are generated:
\end_layout

\begin_layout Itemize
Random setting of stuff rule length (number of equal consecutive stuff bits
 after which stuff bit is inserted).
\end_layout

\begin_layout Itemize
Randomized bit sequence to be stuffed (procedure
\family roman
\shape italic
 generate_bs_settings
\family default
\shape default
).
\end_layout

\begin_layout Itemize
Randomized fact whether at some point, switch from regular to fixed bit
 stuffing will occur ( 
\family roman
\shape italic
set.change_to_fixed
\family default
\shape default
 ).
 Tthis is a typical use-case, because bit stuffing in CAN frame always begin
 with regular stuffing and at some point switches to Fixed bit stuffing.
\end_layout

\begin_layout Itemize
Length of bit sequence which will be stuffed by regular stuff bits (
\family roman
\shape italic
set.bc_non_fixed
\family default
\shape default
) and length which will be stuffed by fixed stuff bits (
\family roman
\shape italic
set.bc_fixed).
\end_layout

\begin_layout Standard
Note that generated bit sequence has higher probability (85 %) of equal
 value between two consecutive bits.
 This precaution makes sure that fair amount of Stuff Bits will be inserted
 and discarded during the test.
\end_layout

\begin_layout Standard
SW model is realized via 
\family roman
\shape italic
calc_sw_bit_stuf_sequence
\family default
\shape default
 procedure which calculates expected bit sequence after bit stuffing in
 
\family roman
\shape italic
set.stuffed_data_seq
\family default
\shape default
 from generated bit sequence 
\family roman
\shape italic
set.tx_data_seq
\family default
\shape default
.
 Output of Bit Stuffing DUT is compared with expected output from model
 after each bit is fed to Bit Stuffing DUT.
 Furthermore, upon insertion of Stuff bit, random bit-flip is added into
 bit stream (
\family roman
\shape italic
err_data
\family default
\shape default
) before bit destuffing and verification of stuff error detection is performed
 (
\family roman
\shape italic
gen_st_error
\family default
\shape default
 process).
\end_layout

\begin_layout Chapter
Reference tests
\end_layout

\begin_layout Standard
Reference tests verify operation of CTU CAN FD with reference controller.
 To achieve this, several sets of random CAN Frames were generated, transmitted
 by reference CAN FD controller, and recorded by logic analyzer.
 Each data set thus contains CAN Frame and according bit sequence which
 was transmitted by reference controller.
 Datasets are stored in dedicated files.
 Generation of CAN frames, transmission by reference controller, control
 of logic analyzer and recording of data sets was executed by auxiliary
 utility Kvaalt Logger implemented in C (located in 
\begin_inset Quotes eld
\end_inset

tools
\begin_inset Quotes erd
\end_inset

 directory).
\end_layout

\begin_layout Standard
The architecture of Reference test is shown in Figure 
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:reference-test-block-diagram"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 First bit rate is configured by 
\family roman
\shape italic
CAN_configure_timing
\family default
\shape default
 procedure.
 At the moment, only one configuration is used (500 Kb/s in 
\shape smallcaps
Nominal Bit-Rate
\shape default
, 2 Mb/s in 
\shape smallcaps
Data Bit-Rate
\shape default
 and 80 % 
\shape smallcaps
Sample Point
\shape default
).
 Then, bit sequence (
\family roman
\shape italic
bit_sequence)
\family default
\shape default
 and CAN frame (
\family roman
\shape italic
TX_frame
\family default
\shape default
) are read from data set by 
\family roman
\shape italic
read_bit_sequence
\family default
\shape default
 function.
 Then bit generator (
\family roman
\shape italic
bit_gen_comp
\family default
\shape default
) is started.
 Bit generator generates this sequence on CAN Bus which is connected to
 CTU CAN FD.
 Upon the end of generation (
\family roman
\shape italic
bit_gen_done = true
\family default
\shape default
), CTU CAN FD should have CAN FD frame received in its RX Buffer.
 Frame is read from CTU CAN FD and compared with generated frame which was
 inserted to reference controller (
\family roman
\shape italic
TX_frame
\family default
\shape default
).
 If there is a mismatch, and error is reported.
\end_layout

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placement H
wide false
sideways false
status open

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\noindent
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\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Reference test block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:reference-test-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Chapter
Unit tests
\end_layout

\begin_layout Standard
CAN FD IP Core is tested in the dedicated testing framework (CANTest) implemente
d in VHDL, TCL and Python.
 It provides automated, randomized and reproducible RTL tests.
 CANTest always follows a simple rule: Each test must have
\series bold
 exact result
\series default
 whether the test passed or failed! VUnit library is used as wrapper, GHDL
 and Modelsim Altera 6.5b are used as target simulators.
 Tests are executed automatically after every merge request to master branch
 of CTU FEE GitLab repository.
 Furthermore, automated test run is available every night.
\end_layout

\begin_layout Standard
All source codes of CANTest are located in 
\series bold
testbench
\series default
 directory.
 CANTest can be started from Linux terminal by running script 
\series bold
run.py <config_name> 
\series default
where <config_name> corresponds to YAML config file with tests that should
 be executed.
 Description of each test and its configuration is shown in following sub-chapte
rs.
 At the moment there are two configurations available:
\end_layout

\begin_layout Description
\begin_inset space \qquad{}
\end_inset

tests_fast.yml Fast test run which is executed on every merge request.
\end_layout

\begin_layout Description
\begin_inset space \qquad{}
\end_inset

tests_nightly.yml Longer test run which is executed once every 24 hours.
\end_layout

\begin_layout Standard
CANTest framework implements 
\series bold
4 types of tests
\series default
:
\end_layout

\begin_layout Description
\begin_inset space \qquad{}
\end_inset

Unit Test each circuit towards its expected functionality.
\end_layout

\begin_layout Description
\begin_inset space \qquad{}
\end_inset

Feature Test functionality of CTU CAN FD as whole in specific situations.
\end_layout

\begin_layout Description
\begin_inset space \qquad{}
\end_inset

Sanity Test implements various bus topologies and simulates bus traffic
 with more controllers.
\end_layout

\begin_layout Description
\begin_inset space \qquad{}
\end_inset

Reference Test verifies communication with existing CAN FD implementations.
\end_layout

\begin_layout Standard
By default, tests are executed via GHDL simulator.
 An example of test command for fast test run is:
\end_layout

\begin_layout Quotation

\series bold
run.py test tests_fast.yml
\end_layout

\begin_layout Standard
To use Modelsim as simulator (for manual debug with graphic wave output),
 following command can be used:
\end_layout

\begin_layout Quotation

\series bold
VUNIT_SIMULATOR=modelsim ./run.py test tests_fast.yml -- -g
\end_layout

\begin_layout Standard
Note that when running simulations with graphic output from remote PC over
 SSH connection 
\begin_inset Quotes eld
\end_inset

-Y
\begin_inset Quotes erd
\end_inset

 argument must be used.
 
\end_layout

\begin_layout Section
VHDL Test libraries
\end_layout

\begin_layout Subsection
CANTestlib.vhd
\end_layout

\begin_layout Standard
CANtestLib.vhd provides set of types and procedures which aim to ease the
 test implementation and debugging.
 CANtestLib provides set of HAL functions which access CTU CAN FD and configure
 its functionality.
 During test implementation, it is recommended to use HAL wrappers as much
 as possible instead of direct register access!
\end_layout

\begin_layout Subsection
randomLib.vhd
\end_layout

\begin_layout Standard
Random lib contains custom functions for generation of random numbers.
 File 
\series bold
randomlib.vhd
\series default
 contains generated array and set of procedures for returning random elements.
 This array of numbers was generated by Matlab and has 
\series bold
Uniform distribution
\series default
 of values from the interval (0,1).
 Functions from the library provide values from generated array in a form
 of std_logic or std_logic vector.
 Additional function (
\family roman
\shape italic
rand_gaus
\family default
\shape default
) provides random numbers with a Gaussian distribution.
 To obtain random element (vector, bit, etc.) signal 
\family roman
\shape italic
rand_ctr
\family default
\shape default
 needs to be provided.
 This signal represents an index of the returned element (from generated
 array) and is automatically increased when the procedure ends.
 Note that this approach provides only pseudo-random number generation,
 but it is sufficient for the purpose of CANTest framework.
 By increasing the size of generated array quality of random number generation
 is also increased.
 Actual size of the generated array is 3000 elements in range 0 to 1.
 There is one major disadvantage of this approach.
 When random number generation is used from several processes, more rand_ctr
 signals are needed.
 Basic test entity has one implicit signal rand_ctr defined for this purpose.
\end_layout

\begin_layout Section
Test entities
\end_layout

\begin_layout Standard
In order to unify all tests of CANTest, 
\family roman
\shape italic
CAN_test
\family default
\shape default
 entity is implemented, and it is described in following table:
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="13" columns="4">
<features tabularvalignment="middle">
<column alignment="left" valignment="top" width="0pt">
<column alignment="left" valignment="top">
<column alignment="left" valignment="top">
<column alignment="left" valignment="top" width="0pt">
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
Source file
\end_layout

\end_inset
</cell>
<cell multicolumn="1" alignment="right" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CANtestLib.vhd
\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
Entity name
\end_layout

\end_inset
</cell>
<cell multicolumn="1" alignment="right" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
CAN_test
\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell multicolumn="1" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
Description
\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell multicolumn="1" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none" width="17cm">
\begin_inset Text

\begin_layout Plain Layout
\noindent
\begin_inset VSpace defskip
\end_inset


\begin_inset Box Frameless
position "t"
hor_pos "c"
has_inner_box 1
inner_pos "t"
use_parbox 1
use_makebox 0
width "95col%"
special "none"
height "1in"
height_special "totalheight"
thickness "0.4pt"
separation "3pt"
shadowsize "4pt"
framecolor "black"
backgroundcolor "none"
status open

\begin_layout Plain Layout
Basic test entity.
 Provides common test parameters for all tests.
 Each test is intended to implement architecture of this entity.
\end_layout

\end_inset


\end_layout

\begin_layout Plain Layout
\noindent
\begin_inset VSpace defskip
\end_inset


\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell multicolumn="1" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\series bold
Ports
\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
<cell multicolumn="2" alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Name
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Direction
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Type
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Description
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
run
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
boolean
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Starting signal for the test
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
iterations
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
natural
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Number of iterations to be executed in one test run
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
log_level
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
log_lvl_type
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Logging severity which should be reported.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
error_beh
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
err_beh_type
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Specifies how does the test behave when error occurs
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
error_tol
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
in
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
natural
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Maximal amount of errors which does not cause test to fail
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
status
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
test_status_type
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Actual status of the test.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\family roman
\shape italic
errors
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
out
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
natural
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error counter of the test
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Section
Common test configuration
\begin_inset CommandInset label
LatexCommand label
name "sec-common-Test-configuration"

\end_inset


\end_layout

\begin_layout Standard
YAML configuration file for test run configuration has several common attributes
 for each test in CANTest framework.
 Note that YAML is tree-like structure, and if config is not specified in
 a node, configuration from upper level of tree-like structure is taken.
 CANTest has following default YAML parameters available:
\end_layout

\begin_layout Description
log_level Logging severity which should be used during the test.
\end_layout

\begin_layout Description
error_tolerance Number of errors that can be tolerated in the test.
 If number of errors exceeds this number, test outcome is evaluated as failed.
 Note that in default configuration of test framework, simulation is stopped
 immediately after report with error severity, thus making this configuration
 parameter redundant.
\end_layout

\begin_layout Description
iterations Number of iterations that should be executed on single test.
 This value corresponds to 
\family roman
\shape italic
iterations
\family default
\shape default
 input of 
\family roman
\shape italic
CAN_test
\family default
\shape default
 entity.
\end_layout

\begin_layout Description
timeout Timeout on length of test run, before VUnit will abort the simulation.
\end_layout

\begin_layout Description
wave TCL file which displays most important signals of DUT in Wave window
 of Modelsim simulator.
 This parameter is used for manual debugging and bring-up of tests.
\end_layout

\begin_layout Section
Code coverage
\end_layout

\begin_layout Standard
GNU lcov engine is used to evaluate code coverage of CTU CAN FD source codes
 and test benches during automated runs in GitLab of CTU FEE.
 Refer to 
\begin_inset Quotes eld
\end_inset

test/Makefile
\begin_inset Quotes erd
\end_inset

 file with following target:
\end_layout

\begin_layout Quote
coverage: 
\end_layout

\begin_deeper
\begin_layout Quote
lcov --capture --directory build --output-file code_coverage.info
\end_layout

\begin_layout Quote
genhtml code_coverage.info --output-directory code_html 
\end_layout

\end_deeper
\begin_layout Standard
An example result of code coverage result is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:Code-coverage-example]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Code-coverage-example"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Code_coverage_example.pdf
	lyxscale 20
	scale 45
	rotateAngle 270

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Code coverage example
\begin_inset CommandInset label
LatexCommand label
name "fig:Code-coverage-example"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Section
Simulator settings
\end_layout

\begin_layout Standard
CANTest framework is using some simulator settings which are not default.
 These settings are required for proper functionality:
\end_layout

\begin_layout Itemize
default time unit is 
\begin_inset Quotes eld
\end_inset

fs
\begin_inset Quotes erd
\end_inset

 instead of 
\begin_inset Quotes eld
\end_inset

ns
\begin_inset Quotes erd
\end_inset

.
 This setting is needed to simulate precise oscillator tolerance!
\end_layout

\begin_layout Section
Unit tests
\end_layout

\begin_layout Standard
Unit tests verify functionality of each circuit on its own, and compare
 it with expected functionality.
 Expected functionality is implemented in behavioral manner (as a circuit
 model or verification function).
 It is important that the circuit implementation and the behavioral model
 of circuit are very well separated, and share as little source code as
 possible! Basic architecture of each unit test is in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:Unit_diagram]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Unit_diagram"

\end_inset

 and can be summed up in following points:
\end_layout

\begin_layout Enumerate
Generate constrained random inputs to DUT (Device Under Test).
\end_layout

\begin_layout Enumerate
Observe circuit function.
\end_layout

\begin_layout Enumerate
Compare outputs of the circuit and outputs of the model or evaluation function.
\end_layout

\begin_layout Enumerate
If a mismatch between model and DUT occurs, increase error counter and report
 error log.
\end_layout

\begin_layout Enumerate
Repeat steps 1 to 4 until a certain number of iterations was reached.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/unit_test_diagram.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Unit test principle
\begin_inset CommandInset label
LatexCommand label
name "fig:Unit_diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Each unit test has its own TCL script which adds the most important wave-forms
 to Wave window of Modelsim simulator.
 This Wave file is used for manual debugging of circuit or a test.
\end_layout

\begin_layout Standard
Each unit test must be located in a separate directory under 
\series bold
unit
\series default
 directory.
 The test directory (e.g CRC) must contain one 
\series bold
VHDL file
\series default
 which implements test architecture.
 TCL file with waveform configurations is optional, and it is mostly used
 for manual debugging of a test or circuit.
 Each unit test requires a separate run of simulator, since each unit test
 implements different DUT, thus simulated architecture is distinct in each
 unit test.
\end_layout

\begin_layout Subsection
How to add new unit test?
\end_layout

\begin_layout Standard
Following steps are recommended when creating new unit test in CANTest:
\end_layout

\begin_layout Enumerate
Create a new folder in unit folder.
\end_layout

\begin_layout Enumerate
Implement test as an architecture of 
\begin_inset Quotes eld
\end_inset

CAN_test
\begin_inset Quotes erd
\end_inset

.
 Note that test 
\series bold
must have 
\begin_inset Quotes eld
\end_inset

_tb
\begin_inset Quotes erd
\end_inset

 suffix
\series default
 in the name of VHDL file.
 It recommended to copy existing test and modify it to cover new functionality.
\end_layout

\begin_layout Enumerate
Copy existing TCL script from some unit test and modify the wave-forms to
 be observed.
\end_layout

\begin_layout Enumerate
Add test to one of configuration files under 
\begin_inset Quotes eld
\end_inset

unit/tests
\begin_inset Quotes erd
\end_inset

.
\end_layout

\begin_layout Subsection
Existing unit tests
\end_layout

\begin_layout Subsubsection
Interrupt Manager
\end_layout

\begin_layout Standard
Testbench generates random interrupt sources at any time by 
\family roman
\shape italic
src_gen
\family default
\shape default
 procedure.
 In each step random Interrupt settings are generated by 
\family roman
\shape italic
generate_commands
\family default
\shape default
 procedure.
 
\family roman
\shape italic
int_emu_proc
\family default
\shape default
 process calculates expected values on 
\family roman
\shape italic
int_out
\family default
\shape default
, 
\family roman
\shape italic
int_vector
\family default
\shape default
, 
\family roman
\shape italic
int_mask
\family default
\shape default
 and 
\family roman
\shape italic
int_ena
\family default
\shape default
 outputs.
 These outputs are compared with DUT output, and error is reported upon
 mismatch between DUT and expected output.
\end_layout

\begin_layout Subsubsection
Message Filter
\end_layout

\begin_layout Standard
Random input frame type and identifier are generated on input of DUT by
 
\family roman
\shape italic
generate_input
\family default
\shape default
 procedure.
 These inputs emulate received frame from CAN Core.
 Random filter settings are generated on Driving Bus by 
\family roman
\shape italic
generate_setting
\family default
\shape default
 procedure.
 Testbench waits for one clock cycle since there is one Flip-Flop on the
 output of Message Filter circuit.
 Then 
\family roman
\shape italic
validate
\family default
\shape default
 function is called, which compares DUT output and expected output.
 
\family roman
\shape italic
validate
\family default
\shape default
 function represents software model of Message Filter.
 If 
\family roman
\shape italic
false
\family default
\shape default
 is returned then an error is detected and reported.
\end_layout

\begin_layout Subsubsection
Prescaler
\end_layout

\begin_layout Standard
Prescaler testbench consists of 3 parts: Testing without 
\shape smallcaps
Resynchronization
\shape default
, Testing with 
\shape smallcaps
Resynchronization
\shape default
 and Testing of 
\shape smallcaps
Bit-Rate Shift
\shape default
.
 All there parts share the same 
\shape smallcaps
Bit-Rate
\shape default
 settings which are generated in the first part of the each test step by
 
\family roman
\shape italic
gen_bit_time_setting
\family default
\shape default
 procedure.
\end_layout

\begin_layout Standard
In the first part, 
\shape smallcaps
Resynchronization
\shape default
 is forbidden.
 Testbench measures number of clock cycles between two consecutive Transmit
 Triggers (which represent the moment of bit transmission, thus measuring
 length of bit) in 
\family roman
\shape italic
check_ctr
\family default
\shape default
 counter.
 Value of this counter is compared with expected value in 
\family roman
\shape italic
exp_dur
\family default
\shape default
.
 Note that value of 
\family roman
\shape italic
check_ctr
\family default
\shape default
 counter is calculated in clock cycles and not 
\shape smallcaps
Time Quanta
\shape default
! Upon mismatch between expected and real length of bit, error is reported.
\end_layout

\begin_layout Standard
In the second part, 
\shape smallcaps
Resynchronization
\shape default
 is allowed, and 
\shape smallcaps
Resynchronization Edges
\shape default
 are generated by 
\family roman
\shape italic
sync_gen_proc
\family default
\shape default
 process.
 Number of clock cycles between two consecutive Transmit Triggers is again
 counted, and compared with expected duration of bit with 
\shape smallcaps
Resynchronization
\shape default
 taken into account.
 Note that since 
\shape smallcaps
Resynchronization
\shape default
 operates on 
\shape smallcaps
Time Quantum,
\shape default
 not clock cycles thus mismatch between expected and real length of bit
 up to value of 
\shape smallcaps
Baud Rate Prescaler
\shape default
 is tolerated.
\end_layout

\begin_layout Standard
In the third part, length of 
\shape smallcaps
Bit Rate Shift
\shape default
 bit and 
\shape smallcaps
CRC Delimiter
\shape default
 bit is calculated, measured and evaluated.
 In 
\shape smallcaps
Bit Rate Shift
\shape default
 bit, 
\shape smallcaps
Bit-Rate
\shape default
 is switched in
\shape smallcaps
 Sample Point
\shape default
 from 
\shape smallcaps
Nominal Bit-Rate
\shape default
 to 
\shape smallcaps
Data Bit-Rate
\shape default
 and in 
\shape smallcaps
CRC Delimiter
\shape default
 bit vice-versa.
 Note that that delay of 2 clock cycles from Sample Trigger is emulated
 on change of 
\shape smallcaps
Bit-Rate
\shape default
 (
\family roman
\shape italic
sample_control
\family default
\shape default
).
 This part of test verifies proper behavior during change of 
\shape smallcaps
Bit-Rate
\shape default
.
\end_layout

\begin_layout Subsubsection
Protocol Control
\end_layout

\begin_layout Standard
Architecture of testbench is shown in a header of testbench itself.
 Random frame is generated on a input of DUT by 
\family roman
\shape italic
CAN_generate_frame
\family default
\shape default
.
 From this frame, expected bit sequence is calculated by 
\family roman
\shape italic
gen_sw_CAN
\family default
\shape default
 procedure.
 After generated frame is applied on the input of DUT, a frame is transmitted
 by DUT1 (
\family roman
\shape italic
tran_frame_valid_in_1
\family default
\shape default
).
 CAN bus level is monitored and transmitted bit sequence is recorded (
\family roman
\shape italic
record_bit_seq
\family default
\shape default
).
 Another DUT (DUT2) receives the frame and sends the 
\shape smallcaps
Acknowledge
\shape default
.
 After the transmission, expected and recorded bit sequence are compared.
 If there is any mismatch error is detected.
 Also, recieved frame (
\family roman
\shape italic
read_frame_from_test_mem
\family default
\shape default
) on the output of DUT2 is compared with original generated frame and mismatch
 also indicates an error.
 Note that transmitted bit sequence does not include 
\shape smallcaps
Stuff Bits
\shape default
, since 
\shape smallcaps
Stuff Bits
\shape default
 are inserted outside of Protocol Control!
\end_layout

\begin_layout Subsubsection
RX Buffer
\end_layout

\begin_layout Standard
RX Buffer unit test simulates received frame as if stored by CAN Core via
 RX Buffer commands.
 A random frame is generated and RX Buffer storing protocol is emulated
 by procedure 
\family roman
\shape italic
insert_frame_to_RX_Buffer
\family default
\shape default
.
 Upon successful storing of frame (
\family roman
\shape italic
rx_data_overrun
\family default
\shape default
 was not activated by DUT), CAN frame is also stored to Input test memory
 (
\family roman
\shape italic
in_mem
\family default
\shape default
) by 
\family roman
\shape italic
insert_frame_test_mem
\family default
\shape default
 procedure.
 Another process 
\family roman
\shape italic
data_reader
\family default
\shape default
 emulates SW, reading frames from RX Buffer, and storing them to Output
 test memory (
\family roman
\shape italic
out_mem
\family default
\shape default
).
 When both memories are filled (
\family roman
\shape italic
in_mem_full
\family default
\shape default
, 
\family roman
\shape italic
out_mem_full
\family default
\shape default
), data consistency checker process compares content of Input test memory
 and Output test memory.
 Upon mismatch, error is reported.
 Note that between two successive frame reads, testbench waits for random
 number of clock cycles by 
\family roman
\shape italic
wait_rand_cycles
\family default
\shape default
.
 This is to guarantee that RX Buffer data overrun will occur in some of
 the situations, and thus verifies proper operation of Data Overrun detection
 logic.
\end_layout

\begin_layout Subsubsection
TX Arbitrator
\end_layout

\begin_layout Standard

\color black
TX Arbitrator unit test models behavior of TXT Buffers by 
\family roman
\shape italic
buf_em_proc
\family default
\shape default
 process.
 This process randomly moves TXT Buffer between FSM states which are ready
 for transmission, and FSM states which are not ready for transmission (
\family roman
\shape italic
txt_buf_ready
\family default
\shape default
 signal).
 Buffers are filled (as if from SW) by 
\family roman
\shape italic
buf_acc_proc
\family default
\shape default
 process with random data.
 Content of Buffer model is stored in 
\family roman
\shape italic
shadow_mem
\family default
\shape default
 signal.
 Function of Priority Decoder is modeled by 
\family roman
\shape italic
prio_dec_model_proc
\family default
\shape default
 process which selects highest priority TXT Buffer in ready state.
 Selection of 
\color inherit

\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[TIMESTAMP_L_W]{TIMESTAMP
\backslash
textunderscore L
\backslash
textunderscore W}
\end_layout

\end_inset

, 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[TIMESTAMP_U_W]{TIMESTAMP
\backslash
textunderscore U
\backslash
textunderscore W}
\end_layout

\end_inset

 and 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[FRAME_FORM_W]{FRAME
\backslash
textunderscore FORM
\backslash
textunderscore W}
\end_layout

\end_inset

 words from TXT Buffer is modeled by 
\family roman
\shape italic
tx_time_proc
\family default
\shape default
 process.
 Delay counter (
\family roman
\shape italic
del_counter
\family default
\shape default
) emulates delay of 6 cycles (3 selection states of TXT Buffer FSM * 2 cycles
 for each state), on the output of TX Arbitrator.
 To model commands from CAN Core on TXT Buffers and TX Arbitrator, 
\family roman
\shape italic
cmd_mod_proc
\family default
\shape default
 process is implemented.
 Lock and Unlock commands of 
\family roman
\shape italic
txt_hw_cmd
\family default
\shape default
 signal are randomly asserted upon presence of valid frame on output of
 DUT (
\family roman
\shape italic
tran_frame_valid_out
\family default
\shape default
).
 Processes which emulates TXT Buffers and CAN Core commands are connected
 to DUT, as well as processes modeling behavior of TX Arbitrator.
 Upon mismatch between outputs of DUT and SW models, error is detected by
 
\family roman
\shape italic
cmp_proc
\family default
\shape default
 process.
 Whole test is managed by 
\family roman
\shape italic
test_proc
\family default
\shape default
 process which generates random TXT Buffer priorities for each test step
 by 
\family roman
\shape italic
set_priorities
\family default
\shape default
 function.
\end_layout

\begin_layout Subsubsection

\color black
TXT Buffer
\end_layout

\begin_layout Standard

\color black
TXT Buffer unit test generates random data as if written by SW in 
\family roman
\shape italic
data_gen_proc
\family default
\shape default
 process.
 In each state where TXT Buffer is accessible, random CAN frame is stored
 to DUT and also to test memory (
\family roman
\shape italic
shadow_mem
\family default
\shape default
) which represents SW model of TXT Buffer.
 Access to TXT Buffer from CAN Core is emulated by 
\family roman
\shape italic
data_read_proc
\family default
\shape default
 process.
 If there is a mismatch between contents of data read from TXT Buffer and
 shadow memory, 
\family roman
\shape italic
data_coh_err_ctr
\family default
\shape default
 signal is set.
 SW and HW commands on TXT Buffer are modeled by commands_proc process which
 evaluates proper function of TXT Buffer FSM, reports error and asserts
 
\family roman
\shape italic
state_coh_error_ctr
\family default
\shape default
 upon upon mismatch.
 Whole unit test is controlled by 
\family roman
\shape italic
test_proc
\family default
\shape default
 process.
\end_layout

\begin_layout Section
Feature tests
\end_layout

\begin_layout Standard
Feature tests examines functionality of CTU CAN FD which is created by cooperati
on of more circuits, and thus can not be tested in a unit test.
 An architecture of feature tests is different than in unit tests.
 First of all, feature tests have only one test environment, located in
 
\begin_inset Quotes eld
\end_inset

test/feature/tb_feature.vhd
\begin_inset Quotes erd
\end_inset

.
 Each feature test is then implemented as VHDL procedure in separate test
 file (e.g.
 test/feature/arbitration_feature_tb.vhd).
 The architecture of this test is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:Feature-test-env]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Feature-test-env"

\end_inset

.
 Two separate CTU CAN FD controllers (
\family roman
\shape italic
CAN_inst
\family default
\shape default
) are instantiated, and connected to CAN Bus in 
\family roman
\shape italic
CAN_feature_test
\family default
\shape default
 entity.
 Fixed transceiver delay is emulated (20 clock cycles) between 
\family roman
\shape italic
CAN_TX
\family default
\shape default
 and 
\family roman
\shape italic
CAN_RX
\family default
\shape default
 pins of CTU CAN FD via 
\family roman
\shape italic
tr_proc
\family default
\shape default
 process.
 Feature tests contain two separate clock sources with 0 ppm and 100 ppm
 oscillator tolerance (
\family roman
\shape italic
p(i).clk_sys
\family default
\shape default
).
 This setting is to make sure that 
\shape smallcaps
Resynchronization
\shape default
 between two CTU CAN FD nodes works properly.
 Each clock source is connected to one CTU CAN FD controller.
 Test interface to this environment is via two Avalon buses (
\family roman
\shape italic
mem_bus(i)
\family default
\shape default
) , one for each CTU CAN FD controller.
 Both nodes in feature test environment are configured with default values
 of Bit time registers.
 It is recommended not to modify this configuration.
 Several existing feature tests rely on default configuration to function
 properly (e.g.
 waiting times).
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/Feature_env.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Feature test environment
\begin_inset CommandInset label
LatexCommand label
name "fig:Feature-test-env"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Standard
Each feature test is implemented in a standalone package.
 This package contains procedure with assignments to memory buses and observatio
ns of bus values or internal signals.
 Each procedure is called from 
\family roman
\shape italic
exec_feature_test
\family default
\shape default
 procedure in main test loop.
 Correct feature test procedure is selected based on the value in 
\family roman
\shape italic
test_name
\family default
\shape default
.
 This signal is set in beginning of each feature test execution.
\end_layout

\begin_layout Subsection
How to add new feature test?
\end_layout

\begin_layout Standard
Following steps must be taken when new feature test is added:
\end_layout

\begin_layout Enumerate
Copy existing feature test to new test file (e.g.
 arbitration_feature_tb.vhd)
\end_layout

\begin_layout Enumerate
Rename the package to have a unique name.
 Rename the procedure in the package accordingly.
 Note that test 
\series bold
must have 
\begin_inset Quotes eld
\end_inset

_tb
\begin_inset Quotes erd
\end_inset

 suffix
\series default
 in the name of VHDL file.
\end_layout

\begin_layout Enumerate
Implement feature test procedure by executing memory accesses to CTU CAN
 FD nodes in feature test environment.
 The variable 
\family roman
\shape italic
outcome
\family default
\shape default
 must be set to 
\family roman
\shape italic
true
\family default
\shape default
 if the test passed, and to 
\family roman
\shape italic
false
\family default
\shape default
 if the test failed.
 One execution of the procedure corresponds to one iteration of the test.
 If error is detected, it is good to report an error, since default behavior
 of actual test framework, is to finish execution upon log with error severity.
\end_layout

\begin_layout Enumerate
Add test name to YAML configuration file under 
\begin_inset Quotes eld
\end_inset

feature/tests
\begin_inset Quotes erd
\end_inset

 configuration.
\end_layout

\begin_layout Subsection
Existing feature tests
\end_layout

\begin_layout Standard
At the moment, following feature test are implemented for CTU CAN FD:
\end_layout

\begin_layout Itemize
abort_transmittion_feature_tb.vhd
\end_layout

\begin_layout Itemize
arbitration_feature_tb.vhd
\end_layout

\begin_layout Itemize
retr_limit_feature_tb.vhd
\end_layout

\begin_layout Itemize
byte_enable_feature_tb.vhd
\end_layout

\begin_layout Itemize
rtr_pref_feature_tb.vhd
\end_layout

\begin_layout Itemize
data_length_code_feature_tb.vhd
\end_layout

\begin_layout Itemize
rx_status_feature_tb.vhd
\end_layout

\begin_layout Itemize
fault_confinement_feature_tb.vhd
\end_layout

\begin_layout Itemize
spec_mode_feature_tb.vhd
\end_layout

\begin_layout Itemize
feature_env_setup.tcl
\end_layout

\begin_layout Itemize
forbid_fd_feature_tb.vhd
\end_layout

\begin_layout Itemize
timestamp_options_feature_tb.vhd
\end_layout

\begin_layout Itemize
interrupt_feature_tb.vhd
\end_layout

\begin_layout Itemize
traf_meas_feature_tb.vhd
\end_layout

\begin_layout Itemize
invalid_configs_feature_tb.vhd
\end_layout

\begin_layout Itemize
tran_delay_feature_tb.vhd
\end_layout

\begin_layout Itemize
overload_feature_tb.vhd
\end_layout

\begin_layout Itemize
tx_arb_time_tran_feature_tb.vhd
\end_layout

\begin_layout Itemize
bus_start_feature_tb.vhd
\end_layout

\begin_layout Standard
Each feature test is described within header of test implementation.
 Each test is described as sequence of steps, which are executed during
 feature test procedure.
 Refer to source code of each test for further description of each test.
\end_layout

\begin_layout Section
Sanity test
\begin_inset CommandInset label
LatexCommand label
name "sec-Sanity-test"

\end_inset


\end_layout

\begin_layout Standard
Sanity test simulates behavior of CTU CAN FD in environment which is close
 to real operation.
 Sanity test consists of 4 CTU CAN FD nodes (
\family roman
\shape italic
node_1_comp
\family default
\shape default
) connected on CAN Bus.
 It can be easily extended to more than 4 nodes.
 Block diagram of sanity test is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:sanity-block-diagram]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:sanity-block-diagram"

\end_inset

.
 Sanity test has following features:
\end_layout

\begin_layout Itemize

\shape smallcaps
Transceiver Delay
\shape default
 modeling
\end_layout

\begin_layout Itemize
Real bus topology
\end_layout

\begin_layout Itemize
Oscillator tolerance simulation
\end_layout

\begin_layout Itemize
Noise generation
\end_layout

\begin_layout Itemize
Traffic emulation and data consistency evaluation
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/sanity_env.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Sanity test block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:sanity-block-diagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Transciever delay
\begin_inset CommandInset label
LatexCommand label
name "subsec-Transciever-delay"

\end_inset


\end_layout

\begin_layout Standard

\family roman
\shape italic
CAN_TX
\family default
\shape default
 and 
\family roman
\shape italic
CAN_RX
\family default
\shape default
 ports of each CTU CAN FD are connected to Signal Delayer components (
\family roman
\shape italic
trv_del_gen_tx_delayer
\family default
\shape default
, 
\family roman
\shape italic
trv_del_gen_rx_delayer
\family default
\shape default
) which delay input signal by certain amount of time (
\family roman
\shape italic
delay
\family default
\shape default
 input).
 This feature is especially important in fast 
\shape smallcaps
Data Bit-Rate
\shape default
 where 
\shape smallcaps
Bit Time
\shape default
 is shorter than 
\shape smallcaps
Transceiver Delay
\shape default
.
 In order to find out how to configure 
\shape smallcaps
Transceiver Delay
\shape default
 refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Sanity-test"
plural "false"
caps "false"
noprefix "false"

\end_inset


\end_layout

\begin_layout Subsection
Bus topology
\begin_inset CommandInset label
LatexCommand label
name "subsec-Real-bus-topology"

\end_inset


\end_layout

\begin_layout Standard
To implement real delays on CAN Bus, Signal Delayer components are used
 in a matrix (
\family roman
\shape italic
i_txdelay
\family default
\shape default
 components), which emulates delay from 
\family roman
\shape italic
CAN_TX
\family default
\shape default
 pin of each CTU CAN FD to 
\family roman
\shape italic
CAN_RX
\family default
\shape default
 pin of each CTU CAN FD.
 Assuming 1 ns equals approximately 20 cm of electric signal transport delay,
 bus lengths have resolution 10 cm.
 Delayed signal from each transciever is connected via AND gate to each
 receiver.
 Length of the delay is given by 
\series bold
Bus Matrix
\series default
:
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $M_{B}=\left[\begin{array}{cccc}
0 & d_{12} & d_{13} & d_{14}\\
d_{21} & 0 & d_{23} & d_{24}\\
d_{31} & d_{32} & 0 & d_{34}\\
d_{41} & d_{42} & d_{43} & 0
\end{array}\right]$
\end_inset


\end_layout

\begin_layout Standard
Where 
\begin_inset Formula $d_{ab}$
\end_inset

 is the delay from the 
\family roman
\shape italic
CAN_TX
\family default
\shape default
 pin 
\begin_inset Quotes eld
\end_inset

a
\begin_inset Quotes erd
\end_inset

 to 
\family roman
\shape italic
CAN_RX
\family default
\shape default
 pin 
\begin_inset Quotes eld
\end_inset

b
\begin_inset Quotes erd
\end_inset

.
 Each row of matrix represents delay from one node to other nodes.
 In general case, Bus Matrix (
\family roman
\shape italic
bus_matrix
\family default
\shape default
) is n*n matrix where 
\begin_inset Quotes eld
\end_inset

n
\begin_inset Quotes erd
\end_inset

 is the amount of CTU CAN FD Controllers on the bus.
 Note that diagonal of Bus Matrix is equal to zero.
 
\shape smallcaps
Transciever Delay
\shape default
 is already modeled before the node is connected to the bus.
 Bus Matrix is symmetrical along its main diagonal.
 Delay from Node A to Node B is equal to delay from Node B to Node A.
 Bus Matrix can describe every configuration of the Bus with N controllers.
 Bus topology in sanity test does not simulate any analog effects, its purpose
 is to simulate delay caused by finite speed of electrical signal propagation.
 In order to simplify the Bus Matrix calculation, most common topologies
 are implemented in sanity test.
\end_layout

\begin_layout Subsubsection
Bus
\end_layout

\begin_layout Standard
Bus topology is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:bus_topology]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:bus_topology"

\end_inset

.
 Bus Matrix for Bus topology is:
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $M_{B}=\left[\begin{array}{cccc}
0 & l_{1} & l_{1}+l_{2} & l_{1}+l_{2}+l_{3}\\
l_{1} & 0 & l_{2} & l_{2}+l_{3}\\
l_{1}+l_{2} & l_{2} & 0 & l_{3}\\
l_{1}+l_{2}+l_{3} & l_{2}+l_{3} & l_{3} & 0
\end{array}\right]$
\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/bus_topology.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Bus topology
\begin_inset CommandInset label
LatexCommand label
name "fig:bus_topology"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsubsection
Star
\end_layout

\begin_layout Standard
Star topology is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:star_topology]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:star_topology"

\end_inset

.
 Bus Matrix for Star topology is :
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $M_{B}=\left[\begin{array}{cccc}
0 & l_{1}+l_{2} & l_{1}+l_{3} & l_{1}+l_{4}\\
l_{1}+l_{2} & 0 & l_{2}+l_{3} & l_{3}+l_{4}\\
l_{1}+l_{3} & l_{2}+l_{3} & 0 & l_{3}+l_{4}\\
l_{1}+l_{4} & l_{2}+l_{4} & l_{3}+l_{4} & 0
\end{array}\right]$
\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/star_topology.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Star topology
\begin_inset CommandInset label
LatexCommand label
name "fig:star_topology"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsubsection
Tree 
\end_layout

\begin_layout Standard
Tree topology is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:tree_topology]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:tree_topology"

\end_inset

.
 Bus Matrix for Tree topology is :
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $M_{B}=\left[\begin{array}{cccc}
0 & l_{1}+l_{2} & l_{1}+l_{3}+l_{5} & l_{1}+l_{4}+l_{5}\\
l_{1}+l_{2} & 0 & l_{2}+l_{3}+l_{5} & l_{2}+l_{4}+l_{5}\\
l_{1}+l_{3}+l_{5} & l_{2}+l_{3}+l_{5} & 0 & l_{3}+l_{4}\\
l_{1}+l_{4}+l_{5} & l_{2}+l_{4}+l_{5} & l_{3}+l_{4} & 0
\end{array}\right]$
\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/tree_topology.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Tree topology
\begin_inset CommandInset label
LatexCommand label
name "fig:tree_topology"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsubsection
Ring 
\end_layout

\begin_layout Standard
Ring topology is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:ring_topology]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:ring_topology"

\end_inset

.
 Bus matrix for Ring topology is :
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $M_{B}=\left[\begin{array}{cccc}
0 & min(l_{1},l_{2}+l_{3}+l_{4}) & min(l_{1}+l_{2},l_{3}+l_{4}) & min(l_{4},l_{1}+l_{2}+l_{3})\\
min(l_{1},l_{2}+l_{3}+l_{4}) & 0 & min(l_{2},l_{1}+l_{3}+l_{4}) & min(l_{2}+l_{3},l_{1}+l_{4})\\
min(l_{1}+l_{2},l_{3}+l_{4}) & min(l_{2},l_{1}+l_{3}+l_{4}) & 0 & min(l_{3},l_{1}+l_{2}+l_{4})\\
min(l_{4},l_{1}+l_{2}+l_{3}) & min(l_{2}+l_{3},l_{1}+l_{4}) & min(l_{3},l_{1}+l_{2}+l_{4}) & 0
\end{array}\right]$
\end_inset


\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Visio_generated/ring_topology.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Ring topology
\begin_inset CommandInset label
LatexCommand label
name "fig:ring_topology"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsubsection
Custom
\end_layout

\begin_layout Standard
In custom topolgy user/tester can set arbitrary values to Bus Matrix.
 Bus Matrix in custom topology is:
\begin_inset Separator latexpar
\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Formula $M_{B}=\left[\begin{array}{cccc}
0 & l_{1} & l_{2} & l_{3}\\
l_{1} & 0 & l_{4} & l_{5}\\
l_{2} & l_{4} & 0 & l_{6}\\
l_{3} & l_{5} & l_{6} & 0
\end{array}\right]$
\end_inset


\end_layout

\begin_layout Subsection
Oscillator tolerance
\begin_inset CommandInset label
LatexCommand label
name "subsec-Oscillator-tollerance"

\end_inset


\end_layout

\begin_layout Standard
Each controller in sanity test environment has separate clock source with
 100 MHz frequency.
 Since oscillators in real devices are not ideal, oscillator tolerance needs
 to be simulated.
 Each controllers clock has its own tolerance in ppm.
 Each tolerance is maximal possible tolerance, that means the clock is generated
 with this error.
 This approach covers the worst possible case that can happen.
 In order to properly simulate oscillator tolerance time resolution, default
 time unit of simulator must be set to 
\begin_inset Quotes eld
\end_inset

fs
\begin_inset Quotes erd
\end_inset

.
 If set to 
\begin_inset Quotes eld
\end_inset

ps
\begin_inset Quotes erd
\end_inset

 or 
\begin_inset Quotes eld
\end_inset

ns
\begin_inset Quotes erd
\end_inset

, error in each clock cycle is lower than shortest time unit, and will be
 rounded to zero and 
\family roman
\shape italic
clk_sys
\family default
\shape default
 of all controllers will have frequency exactly 100 MHz! During the simulation,
 it is possible to check whether oscillator tolerance is used properly.
 If two nodes have different oscillator tolerance, then according input
 timestamp signals should reach different values after simulation runs for
 some time.
 In order to find out how to configure oscillator tolerance refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Sanity-test"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Subsection
Noise generation
\begin_inset CommandInset label
LatexCommand label
name "subsec-Noise-generation"

\end_inset


\end_layout

\begin_layout Standard
In order to simulate glitches on the bus, random binary noise is generated
 on 
\family roman
\shape italic
CAN_RX
\family default
\shape default
 pins of each CTU CAN FD.
 When noise glitch is generated, there is 50 % probability it will be received
 on 
\family roman
\shape italic
CAN_RX
\family default
\shape default
 pin of each CTU CAN FD instance.
 Glitches are not received by all nodes uniquely in order to distinguish
 between global (all nodes receive glitch) and local (only some nodes receive
 glitch) errors.
 Once a glitch is received (signal 
\family roman
\shape italic
noise_force
\family default
\shape default
), unit receives only generated value of noise, thus it is possible to receive
 
\shape smallcaps
Recessive
\shape default
 value when 
\shape smallcaps
Dominant
\shape default
 value is on the bus.
 Noise generator has two parameters: Noise width and Noise gap.
 Noise width is the length of generated glitch.
 Noise gap is time between two generated glitches.
 Noise width follows Gaussian distribution and Noise gap follows Exponential
 distribution.
 Noise generation can be configured by following parameters:
\end_layout

\begin_layout Description
nw_mean Mean value of Noise width (in nanoseconds)
\end_layout

\begin_layout Description
nw_var Variance of Noise width (in nanoseconds)
\end_layout

\begin_layout Description
ng_mean Mean value of Noise gap (in nanoseconds)
\end_layout

\begin_layout Description
ng_var Variance of Noise gap (in nanoseconds)
\end_layout

\begin_layout Standard
Each configuration parameter corresponds to VHDL signal.
 To find out how to configure these parameters refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Sanity-test"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Subsection
Traffic emulation and data consistency evaluation
\begin_inset CommandInset label
LatexCommand label
name "subsec-Traffic-emulation"

\end_inset


\end_layout

\begin_layout Standard
Sanity test generates random CAN frames and inserts these frames to be transmitt
ed on the CAN bus by 
\family roman
\shape italic
node_access_proc
\family default
\shape default
 process.
 Each frame that is inserted to node (
\family roman
\shape italic
CAN_send_frame
\family default
\shape default
), is also inserted to according TX memory (
\family roman
\shape italic
store_frame_to_test_mem
\family default
\shape default
 procedure, 
\family roman
\shape italic
tx_mems
\family default
\shape default
 signal).
 The content of TX memories monitors which frames were sent on the bus.
 Sanity test reads received frames from CAN Nodes (
\family roman
\shape italic
CAN_read_frame
\family default
\shape default
) and stores them into RX memories (
\family roman
\shape italic
store_frame_to_test_mem
\family default
\shape default
 procedure, 
\family roman
\shape italic
rx_mems
\family default
\shape default
 signal).
 After TX memories are filled, traffic generation is finished.
 In order for sanity test to pass, the data consistency must be kept.
 Each frame which was transmitted by any node must be received by all other
 nodes! Contents of TX and RX memories are compared and data consistency
 is evaluated (
\family roman
\shape italic
check_memories
\family default
\shape default
).
 One iteration of Sanity test (with given configuration) can be summed up
 in following steps:
\end_layout

\begin_layout Enumerate
Generate frames and insert them to CAN Nodes.
\end_layout

\begin_layout Enumerate
Wait until all frames are received or unit turned 
\shape smallcaps
Error Passive 
\shape default
(indicates heavily disturbed bus).
\end_layout

\begin_layout Enumerate
Compare TX Memories and RX Memories contents for data consistency.
 If any frame was not properly received or dropped, error is detected and
 test fails.
\end_layout

\begin_layout Subsection
Sanity test configuration
\begin_inset CommandInset label
LatexCommand label
name "subsec-Sanity-test"

\end_inset


\end_layout

\begin_layout Standard
Sanity test can be configured by default YAML config attributes which are
 common for whole CANTest framework and described in 
\begin_inset CommandInset ref
LatexCommand nameref
reference "sec-common-Test-configuration"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
 Apart from these attributes, there are special attributes which are used
 for configuration of sanity test:
\end_layout

\begin_layout Description
topology Bus topology used in this configuration.
 Valid values are : 
\begin_inset Quotes eld
\end_inset

bus
\begin_inset Quotes erd
\end_inset

 , 
\begin_inset Quotes eld
\end_inset

star
\begin_inset Quotes erd
\end_inset

 , 
\begin_inset Quotes eld
\end_inset

tree
\begin_inset Quotes erd
\end_inset

, 
\begin_inset Quotes eld
\end_inset

ring
\begin_inset Quotes erd
\end_inset

.
 For more information about topologies refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Real-bus-topology"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Description
bus_len_v Length of the bus segments 
\begin_inset Formula $l_{1}$
\end_inset

 to 
\begin_inset Formula $l_{6}$
\end_inset

.
 These parameters have a different meaning for each topology.
 Please refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Real-bus-topology"
plural "false"
caps "false"
noprefix "false"

\end_inset

 to find out the exact meaning of these parameters.
 Please note that if a parameter is not used in Bus Matrix then it can have
 arbitrary value.
\end_layout

\begin_layout Description
trv_del_v Transciever delays of each node in multiples of 10 ns (e.g.
 transciever delay = 220 ns , then td(n)=22).
 Refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Transciever-delay"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Description
osc_tol_v Oscillator errors (maximal tolerance) of each node in ppm.
 Refer to 
\begin_inset CommandInset ref
LatexCommand nameref
reference "subsec-Oscillator-tollerance"
plural "false"
caps "false"
noprefix "false"

\end_inset

.
\end_layout

\begin_layout Description
nw_mean Mean value of noise width (ns).
\end_layout

\begin_layout Description
nw_var Variance of noise width (ns).
\end_layout

\begin_layout Description
ng_mean Mean value of gap between two noise glitches (ns).
\end_layout

\begin_layout Description
ng_var Variance of between two noise glitches (ns).
\end_layout

\begin_layout Description
brp 
\shape smallcaps
Baud Rate Prescaler
\shape default
 in 
\shape smallcaps
Nominal Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR]{BTR[BRP]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
brp_fd 
\shape smallcaps
Baud Rate Prescaler
\shape default
 in 
\shape smallcaps
Data Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR_FD]{BTR
\backslash
textunderscore FD[BRP
\backslash
textunderscore FD]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
prop Length of 
\shape smallcaps
Propagation
\shape default
 segment in 
\shape smallcaps
Nominal Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR]{BTR[PROP]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
ph1 Length of 
\shape smallcaps
Phase 1
\shape default
 segment in 
\shape smallcaps
Nominal Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR]{BTR[PH1]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
ph2 Length of 
\shape smallcaps
Phase 2
\shape default
 segment in 
\shape smallcaps
Nominal Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR]{BTR[PH2]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
sjw Length of 
\shape smallcaps
Synchronization Jump Width
\shape default
 in 
\shape smallcaps
Nominal Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR]{BTR[SJW]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
prop_fd Length of 
\shape smallcaps
Propagation
\shape default
 segment in 
\shape smallcaps
Data Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR_FD]{BTR
\backslash
textunderscore FD[PROP
\backslash
textunderscore FD]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
ph1_fd Length of 
\shape smallcaps
Phase 1
\shape default
 segment in 
\shape smallcaps
Data Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR_FD]{BTR
\backslash
textunderscore FD[PH1
\backslash
textunderscore FD]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
ph2_fd Length of 
\shape smallcaps
Phase 2
\shape default
 segment in 
\shape smallcaps
Data Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR_FD]{BTR
\backslash
textunderscore FD[PH2
\backslash
textunderscore FD]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
sjw_fd Length of 
\shape smallcaps
Synchronization Jump Width
\shape default
 in 
\shape smallcaps
Data Bit-Rate
\shape default
.
 Corresponds to 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[BTR_FD]{BTR
\backslash
textunderscore FD[SJW
\backslash
textunderscore FD]}
\end_layout

\end_inset

 register.
\end_layout

\begin_layout Description
desc Description of this configuration.
\end_layout

\begin_layout Standard
Sample screen shot which describes sanity test configuration in YAML file
 is shown in 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[fig:sanity_config_example]{Figure }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "fig:sanity_config_example"

\end_inset

.
\end_layout

\begin_layout Standard
\begin_inset Float figure
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename ../pics/Sanity_cfg.pdf
	lyxscale 20
	scale 70

\end_inset


\end_layout

\begin_layout Plain Layout
\begin_inset Caption Standard

\begin_layout Plain Layout
Sanity test example configuration
\begin_inset CommandInset label
LatexCommand label
name "fig:sanity_config_example"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Chapter
Synthesis
\end_layout

\begin_layout Standard
CTU CAN FD Synthesis was evaluated towards Cyclone V FPGA Family (Intel)
 and Zynq family (Xilinx).
 CTU CAN FD was not synthesized for ASIC production at the moment.
 Design size and performance depends on configuration constants.
 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[tab:synthesis-intel]{Table }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "tab:synthesis-intel"

\end_inset

 shows results for synthesis in Intel Cyclone V family, and 
\begin_inset ERT
status open

\begin_layout Plain Layout


\backslash
hyperref[tab:synthesis-xilinx]{Table }
\end_layout

\end_inset


\begin_inset CommandInset ref
LatexCommand ref
reference "tab:synthesis-xilinx"
plural "false"
caps "false"
noprefix "false"

\end_inset

 shows result for synthesis in Xilinx Zynq family.
\end_layout

\begin_layout Standard
\begin_inset Float table
placement H
wide false
sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="6" columns="8">
<features tabularvalignment="top">
<column alignment="center" valignment="middle" width="1.8cm">
<column alignment="center" valignment="middle" width="1.3cm">
<column alignment="center" valignment="middle" width="2cm">
<column alignment="center" valignment="middle" width="2.6cm">
<column alignment="center" valignment="middle" width="1.5cm">
<column alignment="center" valignment="middle" width="1.5cm">
<column alignment="center" valignment="middle" width="1.5cm">
<column alignment="center" valignment="middle" width="1.5cm">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX Buffer size [words]
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Logger size [events]
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Supported filters [value, range]
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
LUTs
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
LC Registers
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Memory bits
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
ALMs
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Maximal frequency [MHz]
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
32
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
0,0
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2 540
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1 803
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3 584
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1 730
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
95.86
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
256
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2,0
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2 818
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1 974
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10 752
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1 984
\end_layout

\end_inset
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\begin_layout Chapter
FPGA Verification
\end_layout

\begin_layout Standard
The functionality of CAN FD IP Core is verified in real hardware manually
 at the moment.
 Future certification according to ISO 16845-1 2016 is planned in cooperation
 with industrial partners.
 At the moment, core is recommended for FPGA implementation only.
 Build of automated CAN testing network (HIL) is being planned in cooperation
 with CTU FEE.
\end_layout

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CTU CAN FD was communicating with following devices which implement CAN
 FD Protocol:
\end_layout

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CANoe USB/CAN device from Vector Informatik GmbH.
\end_layout

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Open source SJA1000 Implementation by Igor Mohor , from 
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.
\end_layout

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SJA1000 chips from Philips semiconductors.
\end_layout

\begin_layout Itemize
Kvaser Memorator Pro 2xHS v2 which is used for Reference test.
 ISO CAN FD protocol was used.
\end_layout

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Atmel SAMV71 Ultra development board.
 NON ISO CAN FD protocol was used.
\end_layout

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Several Bit-rates were tested during this testing:
\end_layout

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250 kbit/s 
\shape smallcaps
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\shape default
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\shape smallcaps
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\shape smallcaps
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\shape default
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\shape smallcaps
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\end_layout

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\shape smallcaps
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\shape default
, 2 Mbit/s 
\shape smallcaps
Data Bit-Rate.
\end_layout

\begin_layout Standard
Faster bit rates were not examined in real hardware since used transceivers
 did not support bit-rates over 2 Mbit/s (TJA1041 supports only 1 Mbit/s,
 but it has proven to be functional at 2 Mbit/s).
 An experimental test setup is shown in 
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\begin_layout Chapter
Linux driver
\end_layout

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\begin_layout Chapter
Known issues and future work
\end_layout

\begin_layout Standard
CTU CAN FD has many features which are not required by CAN FD specification.
 However there is still room for improvement.
 Following list names possible improvements:
\end_layout

\begin_layout Itemize
Automate design of Driving Bus and Status Bus.
 These would be described in IP-XACT and signal list would be generated
 automatically (including documentation).
 Another approach would be to remove Driving Bus and Status Bus completely
 and use generated structure throughout the design.
\end_layout

\begin_layout Itemize
Generate automated description of tests from headers of testbench source
 code.
\end_layout

\begin_layout Itemize
Extend reference test to also transmission of CAN frame by CTU CAN FD.
 Bit sequence would be also compared with reference sequence (with small
 error allowed).
\end_layout

\begin_layout Itemize
Implement second memory interface on CTU CAN FD.
 This interface would be a master interface and could perform DMA operations
 to/from main memory on transmission/reception.
 Implement additional registers for configuration of DMA engine.
 Add DMA support to Linux driver.
\end_layout

\begin_layout Itemize
Perform standardization of CTU CAN FD according to ISO 16845-1 2016 standard.
\end_layout

\begin_layout Itemize
Implement automatic 
\shape smallcaps
Bit-Rate
\shape default
 detection, either as part of CTU CAN FD or separate module.
 Once the unit would be turned on, it would measure 
\shape smallcaps
Bit-Rate
\shape default
 (e.g.
 over several frames) and provide the results, or even set bus timing registers.
\end_layout

\begin_layout Itemize
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\shape smallcaps
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\shape default
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\shape smallcaps
Bit-Rates
\shape default
.
\end_layout

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\start_of_appendix
Driving bus signals
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6
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drv_ph1_nbt
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Prescaler
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Phase 1 segment length, Nominal bit time
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6
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drv_ph2_nbt
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Prescaler
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Phase 2 segment length, Nominal bit time
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30-33
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4
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drv_prs_dbt
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Prescaler
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Propagation segment length , Data bit time
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34-37
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4
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drv_ph1_dbt
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Prescaler
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Phase 1 segment length, Data bit time
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38-41
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4
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drv_ph2_dbt
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Prescaler
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Phase 2 segment length, Data bit time
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<row>
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42-45
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4
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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drv_sjw_nbt
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

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Prescaler
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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Synchronisation jump width, Nominal bit time
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<row>
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46-49
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4
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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drv_sjw_dbt
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Prescaler
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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\begin_layout Plain Layout
Synchronisation jump width, Data bit time
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<row>
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50-60
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11
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reserved
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-
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-
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<row>
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61-80
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20
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reserved
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-
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-
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<row>
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81-109
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29
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drv_filter_A_mask
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
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\end_inset
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\begin_layout Plain Layout
Mask for filter A
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\end_inset
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<row>
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\begin_inset Text

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110-113
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4
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drv_filter_A_ctrl
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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\begin_inset Text

\begin_layout Plain Layout
Allowed frames for filter A
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<row>
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\begin_inset Text

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114-142
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29
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drv_filter_A_bits
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\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bits to compare for filter A
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\end_inset
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<row>
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171-143
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29
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drv_filter_B_mask
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\begin_layout Plain Layout
Message filter
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\end_inset
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\begin_layout Plain Layout
Mask for filter B
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\end_inset
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<row>
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175-172
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4
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drv_filter_B_ctrl
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\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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\begin_inset Text

\begin_layout Plain Layout
Allowed frames for filter B
\end_layout

\end_inset
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<row>
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204-176
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29
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drv_filter_B_bits
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bits to compare for filter B
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\end_inset
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<row>
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\begin_inset Text

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205-233
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29
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drv_filter_C_mask
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Mask for filter C
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\end_inset
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<row>
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\begin_inset Text

\begin_layout Plain Layout
234-237
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4
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drv_filter_C_ctrl
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Allowed frames for filter C
\end_layout

\end_inset
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<row>
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\begin_inset Text

\begin_layout Plain Layout
238-266
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29
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drv_filter_C_bits
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bits to compare for filter C
\end_layout

\end_inset
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<row>
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\begin_inset Text

\begin_layout Plain Layout
267-270
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4
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drv_filter_ran_ctrl
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Allowed frames for range filter
\end_layout

\end_inset
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<row>
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\begin_inset Text

\begin_layout Plain Layout
271-299
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\begin_layout Plain Layout
29
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
drv_filter_ran_lo_th
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Low range treshold for range filter
\end_layout

\end_inset
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
300-328
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
29
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
drv_filter_ran_hi_th
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
High range treshold for range filter
\end_layout

\end_inset
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
329
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
1
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
drv_filter_ena
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message filter
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Enable applying message filters.
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
330-349
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
29
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
350
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\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_erase_rx
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

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RX Buffer
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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Erase recieved buffer
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\end_inset
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351
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1
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\end_inset
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\begin_inset Text

\begin_layout Plain Layout
reserved
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\end_inset
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\begin_layout Plain Layout
-
\end_layout

\end_inset
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\begin_inset Text

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\end_inset
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352
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\begin_layout Plain Layout
1
\end_layout

\end_inset
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drv_read_start
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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\begin_layout Plain Layout
RX Buffer
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Move to next word in recieve buffer
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\end_inset
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<row>
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353
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1
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\end_inset
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drv_clr_ovr
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\end_inset
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\begin_layout Plain Layout
RX Buffer
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\end_inset
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\begin_layout Plain Layout
Clear Overrun flag
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\end_inset
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<row>
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351-355
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\end_inset
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3
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\end_inset
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\begin_layout Plain Layout
reserved
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

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\end_layout

\end_inset
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<row>
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356
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\end_inset
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\begin_layout Plain Layout
1
\end_layout

\end_inset
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\begin_layout Plain Layout
drv_erase_txt1
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT Buffer 1
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Erase message in TXT 1 buffer
\end_layout

\end_inset
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<row>
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\begin_layout Plain Layout
357
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\end_inset
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<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_store_txt1
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\end_inset
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<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT Buffer 1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Store message in registers into TXT 1 buffer
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="45" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Index
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\end_inset
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<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Width
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\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Name
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Destination unit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal description
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\end_inset
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<row>
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\begin_inset Text

\begin_layout Plain Layout
358
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_erase_txt2
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT Buffer 2
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Erase message in TXT 2 buffer
\end_layout

\end_inset
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<row>
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\begin_layout Plain Layout
359
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_store_txt2
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT Buffer 2
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Store message in registers into TXT2 buffer
\end_layout

\end_inset
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<row>
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360
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
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<row>
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\begin_inset Text

\begin_layout Plain Layout
361
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_allow_txt1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT Arbitrator
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Allow sending messages from TXT1 buffer
\end_layout

\end_inset
</cell>
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<row>
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\begin_inset Text

\begin_layout Plain Layout
362
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_allow_txt2
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TXT Arbitrator
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Allow sending messages from TXT2 buffer
\end_layout

\end_inset
</cell>
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
363-365
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
3
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
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<row>
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\begin_inset Text

\begin_layout Plain Layout
366
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_write_tx
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX Buffer
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
367
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_write_rx
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX Buffer
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
368-371
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
372
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_sam
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bus Synchron.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Tripple sampling for slow speeds
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
373-375
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout

\end_layout

\end_inset
</cell>
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
376
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_bus_err_int_ena
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Interrupt manager
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Enable Bus error interrupt
\end_layout

\end_inset
</cell>
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
377
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_arb_lst_int_ena
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Interrupt manager
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Enable Arbitration lost interrupt
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
378
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_err_pas_int_ena
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Interrupt manager
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Enable Fault confinement state changed interrupt
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
379
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_wake_int_ena
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Interrupt manager
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
380
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_dov_int_ena
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Interrupt manager
\end_layout

\end_inset
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Enable Data overrun interrupt
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Enable Error warning limit reached interrupt
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1
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drv_tx_int_ena
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Interrupt manager
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\end_inset
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Enable sucessfull transcieve interrupt
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1
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drv_rx_int_ena
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Interrupt manager
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Enable logging finished interrupt
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384
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1
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drv_log_fin_int_ena
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Interrupt manager
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Enable sucessfull recieve interrupt
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385
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1
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drv_brs_int_ena
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Interrupt manager
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\end_inset
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Enable bit rate shift interrutpt
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386
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1
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drv_rx_full_int_ena
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Interrupt manager
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Enable interrupt when recieve buffer is full
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387
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1
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drv_int_vect_erase
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Interrupt manager
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\end_inset
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Command to erase interrupt vector
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388-399
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13
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reserved
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-
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-
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400-407
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8
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drv_ewl
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Fault confinement
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Error warning limit (by standard 96)
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408-415
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8
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drv_erp
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Fault confinement
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Error passive treshold (by standard 128)
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<row>
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424-416
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8
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drv_ctr_val
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Fault confinement
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Value for presetting error counter
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<row>
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428-425
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8
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drv_ctr_sel
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Fault confinement
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Control signals, which counters to preset
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<row>
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459-429
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31
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reserved
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-
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-
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<row>
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460
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1
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drv_CAN_fd_ena
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Protocol control
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\end_inset
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Enable recieve of CAN FD frames
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<row>
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461
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1
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drv_rtr_pref
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Protocol control
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\end_inset
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RTR preffered behaviour
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<row>
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462-464
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3
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reserved
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-
\end_layout

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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
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<row>
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465
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1
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drv_retr_lim_ena
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Protocol control
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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\begin_layout Plain Layout
Retransmittion limit of errornous frames is enabled
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<row>
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466-469
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4
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drv_retr_th
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Protocol control
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\end_inset
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\begin_inset Text

\begin_layout Plain Layout
Retransmittion treshold
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<row>
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470
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1
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drv_bus_mon_ena
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Protocol control
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\begin_inset Text

\begin_layout Plain Layout
Bus monitoring mode
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<row>
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471
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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1
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drv_self_test_ena
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\begin_inset Text

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Protocol control
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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\begin_layout Plain Layout
Self Test mode
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<row>
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472
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1
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\end_inset
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drv_abort_tran
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\end_inset
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\begin_inset Text

\begin_layout Plain Layout
Protocol control
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Immediately abort actual transmittion
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<row>
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473
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1
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drv_set_rx_ctr
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\begin_inset Text

\begin_layout Plain Layout
CAN Core
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Preset sucessfully recieved messages counter
\end_layout

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<row>
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474
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

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1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

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drv_set_tx_ctr
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CAN Core
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Preset sucessfully transcieved messages counter
\end_layout

\end_inset
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

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475-506
\end_layout

\end_inset
</cell>
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drv_trig_sof
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drv_trig_arb_lost
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drv_trig_rec_valid
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Trigger on sucesfull recieve
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Trigger on sucesfull transcieve
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drv_trig_ovl
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Event logger
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Trigger on overload frame transcieved
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drv_trig_error
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Event logger
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Trigger on error appeared
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drv_trig_brs
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Event logger
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Trigger on bit rate shifted
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drv_trig_user_write
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Event logger
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Trigger by logic 1 in this signal
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drv_trig_arb_start
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Event logger
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Trigger on Arbitration field start
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drv_trig_contr_start
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Event logger
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Trigger on Control field start
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drv_trig_data_start
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Event logger
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Trigger on Data field start
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563
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drv_trig_crc_start
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Event logger
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Trigger on CRC field start
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drv_trig_ack_rec
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Event logger
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Trigger on acknowledge recieved
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drv_trig_ack_n_rec
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Event logger
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Trigger on acknowledge was not recieved
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<row>
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566
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drv_trig_ewl_reached
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Event logger
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Trigger on error warning limit was reached
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567
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1
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drv_trig_erp_changed
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Event logger
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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Trigger on error passive state changed
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<row>
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568
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1
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drv_trig_tran_start
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Event logger
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
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Trigger on transmittion started
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
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569
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</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_trig_rec_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Trigger on reception started
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
570-579
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
10
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
580
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_sof
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture Start of Frame
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
581
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_arb_lost
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture Arbitration lost
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
582
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_rec_valid
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture that message was recieved valid
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
583
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_tran_valid
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture that message was transcieved valid
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
584
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_ovl
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when overload frame is transmitted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
585
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
crv_cap_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when error appears
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
586
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_brs
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when bit rate is shifted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
587
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_arb_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Arbitration field starts
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
588
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_contr_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Control field starts
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
589
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_data_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Data field starts
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
590
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_crc_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when CRC field starts
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
591
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_ack_rec
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Acknowledge was recieved
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
592
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_ack_n_rec
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Acknowledge was not recieved
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
593
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_ewl_reached
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Error warning limit was reached
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
594
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_erp_changed
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Fault confinement state has changed
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
595
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_tran_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when Transmittion starts
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
596
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_sap_rec_start
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture when reception starts
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
597
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_sync_edge
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture that Synchronisation edge appeared
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
598
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_stuffed
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture that stuff bit was inserted
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
599
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_destuffed
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture that bit was destuffed from stream
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
600
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
drv_cap_ovr
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Event logger
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Capture that data overrun appeared
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
601-609
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
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Bit Stuffing enable
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stat_data_halt
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Bit was stuffed, transmitting should be halted
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Stuff Error appeared
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Bit is destufffed, shouldntbe recorded by Protocol control
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26
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27
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28
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29-31
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3
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\begin_inset Text

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32-60
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
29
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_ident
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transcieved identifier
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
61-64
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_dlc
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transcieved dlc
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
65
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_is_rtr
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transcieved frame is rtr
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
66
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_frame_type
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transcieved frame type (normal or FD frame)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
67
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_ident_type
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transcieved identifier type (basic or extended)
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
68
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_data_ack
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Acknowledge for TXT buffers, TX data are stored in internal buffer
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
69
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_brs
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Transcieved message should shift bitrate
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
70
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_frame_store
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Command to store input frame for transcieve
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="37" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Index
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Width
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Name
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal description
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
71-79
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tx_counter
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
TX error counter
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
80
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
reserved
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
-
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
81-89
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_rx_counter
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
RX error counter
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
90-98
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_error_counter_norm
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error counter for errors appeared in nominal bit rate
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
99-107
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
9
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_error_counter_fd
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Error counter for errors appeared in data bit rate
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
108-109
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
2
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_error_state
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Fault confinement state
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
110
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_form_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Form error appeared
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
111
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_crc_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
CRC error appeared
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
112
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_ack_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Acknowledge error appeared
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
113
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_unknown_state_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Protocol control is in undefined state
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
114
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_bit_stuff_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Bit or Stuff error appeared
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
115
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_first_bit_after
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
116
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_rec_valid
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message was recieved valid
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
117
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_tran_valid
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Message was transcieved valid
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
118
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_const7
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
119
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_const14
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
120
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_transm_error
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Signal not used
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
121-149
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
29
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_rec_ident_type
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Recieved identifier
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
150-153
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
4
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_rec_dlc
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
Recieved data length code
\end_layout

\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
154
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
1
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Plain Layout
stat_rec_is_rtr
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CRC calculation is enabled
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182
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252
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253
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1
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Error warning limit was reached 
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254
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1
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255
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1
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Acknowledge was recieved
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256
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1
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\end_layout

\begin_layout Bibliography
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key "key-1"
literal "true"

\end_inset

CAN with Flexible Data-Rate Specification v 1.0, Robert Bosch GmbH, April
 2012
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-2"
literal "true"

\end_inset

CAN 2.0 Protocol standard, Robert Bosch GmbH, Rev 3.0
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-23"
literal "false"

\end_inset

AMBA Specification (Rev 2.0), ARM Limited 1999.
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-3"
literal "true"

\end_inset

Controller Area Network - Basics, protocols, chips and applications, Prof.
 Dr.-Ing.
 K.
 Etschberger, 2001
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-4"
literal "true"

\end_inset

CRC for CAN with flexible data rate (CAN FD) - Whitepaper
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-20"
literal "true"

\end_inset

Software for Test Platform, DataSheet, Ille Ondrej, Czech Technical University,
 July 2015
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-21"
literal "true"

\end_inset

Implementation of unconventional CAN controller in VHDL, Diploma Thesis,
 Dušan Hamza, Czech technical university, 2013
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-5"
literal "true"

\end_inset

Robustness of a CAN FD Bus System – About Oscillator Tolerance and Edge
 Deviations, Dr.
 Arthur Mutter, Robert Bosch GmbH, 2013
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-6"
literal "true"

\end_inset

SJA1000 Standalone CAN Controller,Philips Semiconductors, January 2000
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-7"
literal "true"

\end_inset

TJA1041 High speed CAN transceiver Rev.
 06, December 2007, NXP Semiconductors
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-8"
literal "true"

\end_inset

ModelSim Advanced verification and debugging SE Command Reference, Mentor
 Graphics, v 6.0 November 2004
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-9"
literal "true"

\end_inset

VHDL guidlines for synthesis, Siemens semiconductor group
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-10"
literal "true"

\end_inset

FPGA prakticky - Realizace číslicových systémů pro hradlová pole, Jakub
 Šťastný, BEN Technická literatura 2011
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-11"
literal "true"

\end_inset

Číslicové systémy a jazyk VHDL , Jiří Pinker, Martin Poupa, BEN Technická
 literatura 2006
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-12"
literal "true"

\end_inset

 Understanding Metastability in FPGAs, ALTERA
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-13"
literal "true"

\end_inset

SAM V71, SMART ARM-based Flash MCU, Preeliminary datasheet, Atmel, February
 2015
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-14"
literal "true"

\end_inset

VHDL Guides , Dr.
 Jayram, Moorkanikara Nageswaran, Department of Computer Science University
 of California, http://www.ics.uci.edu/~jmoorkan/vhdlref/
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-15"
literal "true"

\end_inset

Avalon Interface Specifications,ALTERA March 2015
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-16"
literal "true"

\end_inset

Methods for Testing the FlexRay Start-up Mechanism, Diploma thesis, Martin
 Paták ,Czech Technical University in Prague, 2012
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-17"
literal "true"

\end_inset

TimeQuest Timing Analyzer - Quick Start Tutorial, ALTERA, December 2009
\end_layout

\begin_layout Bibliography
\begin_inset CommandInset bibitem
LatexCommand bibitem
key "key-19"
literal "true"

\end_inset

Implementing Inferred RAM, http://quartushelp.altera.com/14.0/mergedProjects/hdl/vh
dl/vhdl_pro_ram_inferred.htm
\end_layout

\end_body
\end_document
