DpgenAnd2

• Name : DpgenAnd2 - And2 Macro-Generator
• Synopsys :

  Generate ( 'DpgenAnd2', modelname
           , param = { 'nbit'       : n
                     , 'drive'      : d
                     , 'physical'   : True
                     , 'behavioral' : True
                     }
           )
  

• Description : Generates a n bits two inputs AND with an output power of d named modelname.
• Terminal Names :
  • i0 : input (n bits)
  • i1 : input (n bits)
  • q : output (n bits)
  • vdd : power
  • vss : ground
• Parameters : Parameters are given in the map param.
  • nbit (mandatory) : Defines the size of the generator
  • drive (optional) : Defines the output power of the gates
    • Valid drive are : 2 or 4
    • If this parameter is not defined, it's value is the smallest one permitted
  • physical (optional, default value : False) : In order to generate a layout
  • behavioral (optional, default value : False) : In order to generate a behavior
• Behavior :

  nq <= i0 and i1
  

• Example :

  from stratus import *
  
  class inst_and2 ( Model ) :
  
    def Interface ( self ) :
      self.in1 = SignalIn  ( "in1", 8 )
      self.in2 = SignalIn  ( "in2", 8 )
      self.out = SignalOut (   "o", 8 )
  
      self.vdd = VddIn ( "vdd" )
      self.vss = VssIn ( "vss" )
      
    def Netlist ( self ) :
      Generate ( 'DpgenAnd2', 'and2_8'
               , param = { 'nbit'     : 8
                         , 'physical' : True
                         }
               )      
      self.I = Inst ( 'and2_8', 'inst'
                    , map = { 'i0'  : self.in1
                            , 'i1'  : self.in2
                            , 'q'   : self.out
                            , 'vdd' : self.vdd
                            , 'vss' : self.vss
                            }
                    )
      
    def Layout ( self ) :
      Place ( self.I, NOSYM, Ref(0, 0) )