|
| | OPCODE_CEIL_DECLARE (IADD_RS, NULL) |
| | OPCODE_CEIL_DECLARE (IADD_M, IADD_RS) |
| | OPCODE_CEIL_DECLARE (ISUB_R, IADD_M) |
| | OPCODE_CEIL_DECLARE (ISUB_M, ISUB_R) |
| | OPCODE_CEIL_DECLARE (IMUL_R, ISUB_M) |
| | OPCODE_CEIL_DECLARE (IMUL_M, IMUL_R) |
| | OPCODE_CEIL_DECLARE (IMULH_R, IMUL_M) |
| | OPCODE_CEIL_DECLARE (IMULH_M, IMULH_R) |
| | OPCODE_CEIL_DECLARE (ISMULH_R, IMULH_M) |
| | OPCODE_CEIL_DECLARE (ISMULH_M, ISMULH_R) |
| | OPCODE_CEIL_DECLARE (IMUL_RCP, ISMULH_M) |
| | OPCODE_CEIL_DECLARE (INEG_R, IMUL_RCP) |
| | OPCODE_CEIL_DECLARE (IXOR_R, INEG_R) |
| | OPCODE_CEIL_DECLARE (IXOR_M, IXOR_R) |
| | OPCODE_CEIL_DECLARE (IROR_R, IXOR_M) |
| | OPCODE_CEIL_DECLARE (IROL_R, IROR_R) |
| | OPCODE_CEIL_DECLARE (ISWAP_R, IROL_R) |
| | OPCODE_CEIL_DECLARE (FSWAP_R, ISWAP_R) |
| | OPCODE_CEIL_DECLARE (FADD_R, FSWAP_R) |
| | OPCODE_CEIL_DECLARE (FADD_M, FADD_R) |
| | OPCODE_CEIL_DECLARE (FSUB_R, FADD_M) |
| | OPCODE_CEIL_DECLARE (FSUB_M, FSUB_R) |
| | OPCODE_CEIL_DECLARE (FSCAL_R, FSUB_M) |
| | OPCODE_CEIL_DECLARE (FMUL_R, FSCAL_R) |
| | OPCODE_CEIL_DECLARE (FDIV_M, FMUL_R) |
| | OPCODE_CEIL_DECLARE (FSQRT_R, FDIV_M) |
| | OPCODE_CEIL_DECLARE (CBRANCH, FSQRT_R) |
| | OPCODE_CEIL_DECLARE (CFROUND, CBRANCH) |
| | OPCODE_CEIL_DECLARE (ISTORE, CFROUND) |
| | OPCODE_CEIL_DECLARE (NOP, ISTORE) |
| bool | isZeroOrPowerOf2 (uint64_t x) |
| template<class Allocator> |
| void | deallocCache (randomx_cache *cache) |
| template void | deallocCache< DefaultAllocator > (randomx_cache *cache) |
| template void | deallocCache< LargePageAllocator > (randomx_cache *cache) |
| void | initCache (randomx_cache *cache, const void *key, size_t keySize) |
| void | initCacheCompile (randomx_cache *cache, const void *key, size_t keySize) |
| static uint8_t * | getMixBlock (uint64_t registerValue, uint8_t *memory) |
| void | initDatasetItem (randomx_cache *cache, uint8_t *out, uint64_t itemNumber) |
| void | initDataset (randomx_cache *cache, uint8_t *dataset, uint32_t startItem, uint32_t endItem) |
| template<class Allocator> |
| void | deallocDataset (randomx_dataset *dataset) |
| randomx_argon2_impl * | selectArgonImpl (randomx_flags flags) |
| template<typename T> |
| static constexpr size_t | Log2 (T value) |
| constexpr int | maskLog2 (uint32_t x, int prev) |
| constexpr int32_t | unsigned32ToSigned2sCompl (uint32_t x) |
| constexpr int | rvrd (int reg) |
| constexpr int | rvrs1 (int reg) |
| constexpr int | rvrs2 (int reg) |
| constexpr int | rvcrs (int reg) |
| constexpr uint32_t | rvi (uint32_t op, int rd, int rs1, int rs2=0) |
| constexpr uint16_t | rvc (uint16_t op, int rd, int rs) |
| constexpr uint16_t | rvc (uint16_t op, int imm5, int rd, int imm40) |
| constexpr int | regR (int reg) |
| constexpr int | regLoA (int reg) |
| constexpr int | regHiA (int reg) |
| constexpr int | regLoF (int reg) |
| constexpr int | regHiF (int reg) |
| constexpr int | regLoE (int reg) |
| constexpr int | regHiE (int reg) |
| constexpr int | regRcp (int reg) |
| constexpr int | regRcpF (int reg) |
| constexpr int | regSS (int reg) |
| static void | clearCache (CodeBuffer &buf) |
| static void | emitImm32 (CodeBuffer &buf, int32_t imm, int dst, int src=0, int tmp=0) |
| static void | genAddressRegImm (CodeBuffer &buf, const Instruction &isn) |
| static void | genAddressReg (CodeBuffer &buf, const Instruction &isn) |
| static void | loadFromScratchpad (CodeBuffer &buf, const Instruction &isn) |
| static void | genAddressRegDst (CodeBuffer &buf, const Instruction &isn) |
| static void | emitRcpLiteral1 (CodeBuffer &buf, uint64_t literal) |
| static void | emitRcpLiteral2 (CodeBuffer &buf, uint64_t literal, int32_t numLiterals) |
| static void | emitJump (CodeBuffer &buf, int dst, int32_t codePos, int32_t targetPos) |
| static void | emitInstruction (CompilerState &state, Instruction isn, int i) |
| static void | emitProgramPrefix (CompilerState &state, Program &prog, ProgramConfiguration &pcfg) |
| static void | emitProgramSuffix (CompilerState &state, ProgramConfiguration &pcfg) |
| static void | generateSuperscalarCode (CodeBuffer &buf, Instruction isn, const std::vector< uint64_t > &reciprocalCache) |
| static void | v1_IADD_RS (HANDLER_ARGS) |
| static void | v1_IADD_M (HANDLER_ARGS) |
| static void | v1_ISUB_R (HANDLER_ARGS) |
| static void | v1_ISUB_M (HANDLER_ARGS) |
| static void | v1_IMUL_R (HANDLER_ARGS) |
| static void | v1_IMUL_M (HANDLER_ARGS) |
| static void | v1_IMULH_R (HANDLER_ARGS) |
| static void | v1_IMULH_M (HANDLER_ARGS) |
| static void | v1_ISMULH_R (HANDLER_ARGS) |
| static void | v1_ISMULH_M (HANDLER_ARGS) |
| static void | v1_IMUL_RCP (HANDLER_ARGS) |
| static void | v1_INEG_R (HANDLER_ARGS) |
| static void | v1_IXOR_R (HANDLER_ARGS) |
| static void | v1_IXOR_M (HANDLER_ARGS) |
| static void | v1_IROR_R (HANDLER_ARGS) |
| static void | v1_IROL_R (HANDLER_ARGS) |
| static void | v1_ISWAP_R (HANDLER_ARGS) |
| static void | v1_FSWAP_R (HANDLER_ARGS) |
| static void | v1_FADD_R (HANDLER_ARGS) |
| static void | v1_FADD_M (HANDLER_ARGS) |
| static void | v1_FSUB_R (HANDLER_ARGS) |
| static void | v1_FSUB_M (HANDLER_ARGS) |
| static void | v1_FSCAL_R (HANDLER_ARGS) |
| static void | v1_FMUL_R (HANDLER_ARGS) |
| static void | v1_FDIV_M (HANDLER_ARGS) |
| static void | v1_FSQRT_R (HANDLER_ARGS) |
| static void | v1_CBRANCH (HANDLER_ARGS) |
| static void | v1_CFROUND (HANDLER_ARGS) |
| static void | v1_ISTORE (HANDLER_ARGS) |
| static void | v1_NOP (HANDLER_ARGS) |
| static bool | isMultiplication (SuperscalarInstructionType type) |
| static bool | selectRegister (std::vector< int > &availableRegisters, Blake2Generator &gen, int ®) |
| template<bool commit> |
| static int | scheduleUop (ExecutionPort::type uop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle) |
| template<bool commit> |
| static int | scheduleMop (const MacroOp &mop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle, int depCycle) |
| void | generateSuperscalar (SuperscalarProgram &prog, Blake2Generator &gen) |
| void | executeSuperscalar (int_reg_t(&r)[8], SuperscalarProgram &prog, std::vector< uint64_t > *reciprocals) |
| static uint64_t | getSmallPositiveFloatBits (uint64_t entropy) |
| static uint64_t | getStaticExponent (uint64_t entropy) |
| static uint64_t | getFloatMask (uint64_t entropy) |
|
| static const char * | regR [] = { "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" } |
| static const char * | regR32 [] = { "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" } |
| static const char * | regFE [] = { "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" } |
| static const char * | regF [] = { "xmm0", "xmm1", "xmm2", "xmm3" } |
| static const char * | regE [] = { "xmm4", "xmm5", "xmm6", "xmm7" } |
| static const char * | regA [] = { "xmm8", "xmm9", "xmm10", "xmm11" } |
| static const char * | tempRegx = "xmm12" |
| static const char * | mantissaMaskReg = "xmm13" |
| static const char * | exponentMaskReg = "xmm14" |
| static const char * | scaleMaskReg = "xmm15" |
| static const char * | regIc = "rbx" |
| static const char * | regIc32 = "ebx" |
| static const char * | regIc8 = "bl" |
| static const char * | regScratchpadAddr = "rsi" |
| constexpr int | maxSeedSize = 60 |
| constexpr int | ceil_NULL = 0 |
| constexpr int | wtSum |
| constexpr uint32_t | ArgonBlockSize = 1024 |
| constexpr int | ArgonSaltSize = sizeof("" RANDOMX_ARGON_SALT) - 1 |
| constexpr int | SuperscalarMaxSize = 3 * RANDOMX_SUPERSCALAR_LATENCY + 2 |
| constexpr size_t | CacheLineSize = RANDOMX_DATASET_ITEM_SIZE |
| constexpr int | ScratchpadSize = RANDOMX_SCRATCHPAD_L3 |
| constexpr uint32_t | CacheLineAlignMask = (RANDOMX_DATASET_BASE_SIZE - 1) & ~(CacheLineSize - 1) |
| constexpr uint32_t | CacheSize = RANDOMX_ARGON_MEMORY * ArgonBlockSize |
| constexpr uint64_t | DatasetSize = RANDOMX_DATASET_BASE_SIZE + RANDOMX_DATASET_EXTRA_SIZE |
| constexpr uint32_t | DatasetExtraItems = RANDOMX_DATASET_EXTRA_SIZE / RANDOMX_DATASET_ITEM_SIZE |
| constexpr uint32_t | ConditionMask = ((1 << RANDOMX_JUMP_BITS) - 1) |
| constexpr int | ConditionOffset = RANDOMX_JUMP_OFFSET |
| constexpr int | StoreL3Condition = 14 |
| constexpr bool | trace = false |
| constexpr uint32_t | ScratchpadL1 = RANDOMX_SCRATCHPAD_L1 / sizeof(int_reg_t) |
| constexpr uint32_t | ScratchpadL2 = RANDOMX_SCRATCHPAD_L2 / sizeof(int_reg_t) |
| constexpr uint32_t | ScratchpadL3 = RANDOMX_SCRATCHPAD_L3 / sizeof(int_reg_t) |
| constexpr int | ScratchpadL1Mask = (ScratchpadL1 - 1) * 8 |
| constexpr int | ScratchpadL2Mask = (ScratchpadL2 - 1) * 8 |
| constexpr int | ScratchpadL1Mask16 = (ScratchpadL1 / 2 - 1) * 16 |
| constexpr int | ScratchpadL2Mask16 = (ScratchpadL2 / 2 - 1) * 16 |
| constexpr int | ScratchpadL3Mask = (ScratchpadL3 - 1) * 8 |
| constexpr int | ScratchpadL3Mask64 = (ScratchpadL3 / 8 - 1) * 64 |
| constexpr int | RegistersCount = 8 |
| constexpr int | RegisterCountFlt = RegistersCount / 2 |
| constexpr int | RegisterNeedsDisplacement = 5 |
| constexpr int | RegisterNeedsSib = 4 |
| constexpr int | mantissaSize = 52 |
| constexpr int | exponentSize = 11 |
| constexpr uint64_t | mantissaMask = (1ULL << mantissaSize) - 1 |
| constexpr uint64_t | exponentMask = (1ULL << exponentSize) - 1 |
| constexpr int | exponentBias = 1023 |
| constexpr int | dynamicExponentBits = 4 |
| constexpr int | staticExponentBits = 4 |
| constexpr uint64_t | constExponentBits = 0x300 |
| constexpr uint64_t | dynamicMantissaMask = (1ULL << (mantissaSize + dynamicExponentBits)) - 1 |
| constexpr uint64_t | superscalarMul0 = 6364136223846793005ULL |
| constexpr uint64_t | superscalarAdd1 = 9298411001130361340ULL |
| constexpr uint64_t | superscalarAdd2 = 12065312585734608966ULL |
| constexpr uint64_t | superscalarAdd3 = 9306329213124626780ULL |
| constexpr uint64_t | superscalarAdd4 = 5281919268842080866ULL |
| constexpr uint64_t | superscalarAdd5 = 10536153434571861004ULL |
| constexpr uint64_t | superscalarAdd6 = 3398623926847679864ULL |
| constexpr uint64_t | superscalarAdd7 = 9549104520008361294ULL |
| static const size_t | CodeSize = ((uint8_t*)randomx_init_dataset_aarch64_end) - ((uint8_t*)randomx_program_aarch64) |
| static const size_t | MainLoopBegin = ((uint8_t*)randomx_program_aarch64_main_loop) - ((uint8_t*)randomx_program_aarch64) |
| static const size_t | PrologueSize = ((uint8_t*)randomx_program_aarch64_vm_instructions) - ((uint8_t*)randomx_program_aarch64) |
| static const size_t | ImulRcpLiteralsEnd = ((uint8_t*)randomx_program_aarch64_imul_rcp_literals_end) - ((uint8_t*)randomx_program_aarch64) |
| static const size_t | CalcDatasetItemSize |
| constexpr uint32_t | IntRegMap [8] = { 4, 5, 6, 7, 12, 13, 14, 15 } |
| constexpr size_t | MaxRandomXInstrCodeSize = 56 |
| constexpr size_t | MaxSuperscalarInstrSize = 12 |
| constexpr size_t | SuperscalarProgramHeader = 136 |
| constexpr size_t | CodeAlign = 4096 |
| constexpr size_t | LiteralPoolSize = CodeAlign |
| constexpr size_t | SuperscalarLiteraPoolSize = RANDOMX_CACHE_ACCESSES * CodeAlign |
| constexpr size_t | ReserveCodeSize = CodeAlign |
| constexpr size_t | RandomXCodeSize = alignSize(LiteralPoolSize + ReserveCodeSize + MaxRandomXInstrCodeSize * RANDOMX_PROGRAM_SIZE, CodeAlign) |
| constexpr size_t | SuperscalarSize = alignSize(SuperscalarLiteraPoolSize + ReserveCodeSize + (SuperscalarProgramHeader + MaxSuperscalarInstrSize * SuperscalarMaxSize) * RANDOMX_CACHE_ACCESSES, CodeAlign) |
| constexpr uint32_t | ExecutableSize = CodeSize - LiteralPoolSize |
| constexpr int32_t | LiteralPoolOffset = LiteralPoolSize / 2 |
| constexpr int32_t | SuperScalarLiteralPoolOffset = RandomXCodeSize |
| constexpr int32_t | SuperScalarLiteralPoolRefOffset = RandomXCodeSize + (RANDOMX_CACHE_ACCESSES - 1) * LiteralPoolSize + LiteralPoolOffset |
| constexpr int32_t | SuperScalarHashOffset = SuperScalarLiteralPoolOffset + SuperscalarLiteraPoolSize |
| constexpr int | MaskL1Shift = 32 - maskLog2(RANDOMX_SCRATCHPAD_L1, 0) |
| constexpr int | MaskL2Shift = 32 - maskLog2(RANDOMX_SCRATCHPAD_L2, 0) |
| constexpr int | MaskL3Shift = 32 - maskLog2(RANDOMX_SCRATCHPAD_L3, 0) |
| constexpr int | RcpLiteralsOffset = 144 |
| constexpr int | LiteralPoolReg = 3 |
| constexpr int | SpadReg = 5 |
| constexpr int | DataReg = 6 |
| constexpr int | SuperscalarReg = 7 |
| constexpr int | SshTmp1Reg = 28 |
| constexpr int | SshTmp2Reg = 29 |
| constexpr int | SshPoolReg = 30 |
| constexpr int | SshRcpReg = 31 |
| constexpr int | Tmp1Reg = 8 |
| constexpr int | Tmp2Reg = 9 |
| constexpr int | Tmp1RegF = 24 |
| constexpr int | Tmp2RegF = 25 |
| constexpr int | MaskL1Reg = 10 |
| constexpr int | MaskL2Reg = 11 |
| constexpr int | MaskFscalReg = 12 |
| constexpr int | MaskEclear = 13 |
| constexpr int | MaskEsetLo = 14 |
| constexpr int | MaskEsetHi = 15 |
| constexpr int | MaskL3Reg = 1 |
| constexpr int | ReturnReg = 1 |
| constexpr int | SpAddr0Reg = 26 |
| constexpr int | OffsetXC = -8 |
| constexpr int | OffsetR = 16 |
| constexpr int | OffsetF = 0 |
| constexpr int | OffsetE = 8 |
| constexpr int | OffsetA = 16 |
| constexpr int | OffsetRcp = 28 |
| constexpr int | OffsetRcpF = 22 |
| constexpr int | OffsetSsh = 8 |
| static const uint8_t * | codeLiterals = (uint8_t*)&randomx_riscv64_literals |
| static const uint8_t * | codeLiteralsEnd = (uint8_t*)&randomx_riscv64_literals_end |
| static const uint8_t * | codeDataInit = (uint8_t*)&randomx_riscv64_data_init |
| static const uint8_t * | codeFixDataCall = (uint8_t*)&randomx_riscv64_fix_data_call |
| static const uint8_t * | codePrologue = (uint8_t*)&randomx_riscv64_prologue |
| static const uint8_t * | codeLoopBegin = (uint8_t*)&randomx_riscv64_loop_begin |
| static const uint8_t * | codeDataRead = (uint8_t*)&randomx_riscv64_data_read |
| static const uint8_t * | codeDataReadLight = (uint8_t*)&randomx_riscv64_data_read_light |
| static const uint8_t * | codeFixLoopCall = (uint8_t*)&randomx_riscv64_fix_loop_call |
| static const uint8_t * | codeSpadStore = (uint8_t*)&randomx_riscv64_spad_store |
| static const uint8_t * | codeSpadStoreHardAes = (uint8_t*)&randomx_riscv64_spad_store_hardaes |
| static const uint8_t * | codeSpadStoreSoftAes = (uint8_t*)&randomx_riscv64_spad_store_softaes |
| static const uint8_t * | codeLoopEnd = (uint8_t*)&randomx_riscv64_loop_end |
| static const uint8_t * | codeFixContinueLoop = (uint8_t*)&randomx_riscv64_fix_continue_loop |
| static const uint8_t * | codeEpilogue = (uint8_t*)&randomx_riscv64_epilogue |
| static const uint8_t * | codeSoftAes = (uint8_t*)&randomx_riscv64_softaes |
| static const uint8_t * | codeProgramEnd = (uint8_t*)&randomx_riscv64_program_end |
| static const uint8_t * | codeSshInit = (uint8_t*)&randomx_riscv64_ssh_init |
| static const uint8_t * | codeSshLoad = (uint8_t*)&randomx_riscv64_ssh_load |
| static const uint8_t * | codeSshPrefetch = (uint8_t*)&randomx_riscv64_ssh_prefetch |
| static const uint8_t * | codeSshEnd = (uint8_t*)&randomx_riscv64_ssh_end |
| static const int32_t | sizeLiterals = codeLiteralsEnd - codeLiterals |
| static const int32_t | sizeDataInit = codePrologue - codeDataInit |
| static const int32_t | sizePrologue = codeLoopBegin - codePrologue |
| static const int32_t | sizeLoopBegin = codeDataRead - codeLoopBegin |
| static const int32_t | sizeDataRead = codeDataReadLight - codeDataRead |
| static const int32_t | sizeDataReadLight = codeSpadStore - codeDataReadLight |
| static const int32_t | sizeSpadStore = codeSpadStoreHardAes - codeSpadStore |
| static const int32_t | sizeSpadStoreSoftAes = codeLoopEnd - codeSpadStoreSoftAes |
| static const int32_t | sizeLoopEnd = codeEpilogue - codeLoopEnd |
| static const int32_t | sizeEpilogue = codeSoftAes - codeEpilogue |
| static const int32_t | sizeSoftAes = codeProgramEnd - codeSoftAes |
| static const int32_t | sizeSshInit = codeSshLoad - codeSshInit |
| static const int32_t | sizeSshLoad = codeSshPrefetch - codeSshLoad |
| static const int32_t | sizeSshPrefetch = codeSshEnd - codeSshPrefetch |
| static const int32_t | offsetFixDataCall = codeFixDataCall - codeDataInit |
| static const int32_t | offsetFixLoopCall = codeFixLoopCall - codeDataReadLight |
| static const int32_t | offsetFixContinueLoop = codeFixContinueLoop - codeLoopEnd |
| static const int32_t | LoopTopPos = LiteralPoolSize + sizeDataInit + sizePrologue |
| static const int32_t | RandomXCodePos = LoopTopPos + sizeLoopBegin |
| constexpr int32_t | superScalarHashOffset = RandomXCodeSize |
| const uint8_t * | codeLoopLoad = ADDR(randomx_program_loop_load) |
| const uint8_t * | codeProgamStart = ADDR(randomx_program_start) |
| const uint8_t * | codeReadDataset = ADDR(randomx_program_read_dataset) |
| const uint8_t * | codeReadDatasetLightSshInit = ADDR(randomx_program_read_dataset_sshash_init) |
| const uint8_t * | codeReadDatasetLightSshFin = ADDR(randomx_program_read_dataset_sshash_fin) |
| const uint8_t * | codeDatasetInit = ADDR(randomx_dataset_init) |
| const uint8_t * | codeLoopStore = ADDR(randomx_program_loop_store) |
| const uint8_t * | codeShhLoad = ADDR(randomx_sshash_load) |
| const uint8_t * | codeShhPrefetch = ADDR(randomx_sshash_prefetch) |
| const uint8_t * | codeShhEnd = ADDR(randomx_sshash_end) |
| const uint8_t * | codeShhInit = ADDR(randomx_sshash_init) |
| const int32_t | prologueSize = codeLoopBegin - codePrologue |
| const int32_t | loopLoadSize = codeProgamStart - codeLoopLoad |
| const int32_t | readDatasetSize = codeReadDatasetLightSshInit - codeReadDataset |
| const int32_t | readDatasetLightInitSize = codeReadDatasetLightSshFin - codeReadDatasetLightSshInit |
| const int32_t | readDatasetLightFinSize = codeLoopStore - codeReadDatasetLightSshFin |
| const int32_t | loopStoreSize = codeLoopEnd - codeLoopStore |
| const int32_t | datasetInitSize = codeEpilogue - codeDatasetInit |
| const int32_t | epilogueSize = codeShhLoad - codeEpilogue |
| const int32_t | codeSshLoadSize = codeShhPrefetch - codeShhLoad |
| const int32_t | codeSshPrefetchSize = codeShhEnd - codeShhPrefetch |
| const int32_t | codeSshInitSize = codeProgramEnd - codeShhInit |
| const int32_t | epilogueOffset = CodeSize - epilogueSize |
| static const uint8_t | REX_ADD_RR [] = { 0x4d, 0x03 } |
| static const uint8_t | REX_ADD_RM [] = { 0x4c, 0x03 } |
| static const uint8_t | REX_SUB_RR [] = { 0x4d, 0x2b } |
| static const uint8_t | REX_SUB_RM [] = { 0x4c, 0x2b } |
| static const uint8_t | REX_MOV_RR [] = { 0x41, 0x8b } |
| static const uint8_t | REX_MOV_RR64 [] = { 0x49, 0x8b } |
| static const uint8_t | REX_MOV_R64R [] = { 0x4c, 0x8b } |
| static const uint8_t | REX_IMUL_RR [] = { 0x4d, 0x0f, 0xaf } |
| static const uint8_t | REX_IMUL_RRI [] = { 0x4d, 0x69 } |
| static const uint8_t | REX_IMUL_RM [] = { 0x4c, 0x0f, 0xaf } |
| static const uint8_t | REX_MUL_R [] = { 0x49, 0xf7 } |
| static const uint8_t | REX_MUL_M [] = { 0x48, 0xf7 } |
| static const uint8_t | REX_81 [] = { 0x49, 0x81 } |
| static const uint8_t | AND_EAX_I = 0x25 |
| static const uint8_t | MOV_EAX_I = 0xb8 |
| static const uint8_t | MOV_RAX_I [] = { 0x48, 0xb8 } |
| static const uint8_t | MOV_RCX_I [] = { 0x48, 0xb9 } |
| static const uint8_t | REX_LEA [] = { 0x4f, 0x8d } |
| static const uint8_t | REX_MUL_MEM [] = { 0x48, 0xf7, 0x24, 0x0e } |
| static const uint8_t | REX_IMUL_MEM [] = { 0x48, 0xf7, 0x2c, 0x0e } |
| static const uint8_t | REX_SHR_RAX [] = { 0x48, 0xc1, 0xe8 } |
| static const uint8_t | RAX_ADD_SBB_1 [] = { 0x48, 0x83, 0xC0, 0x01, 0x48, 0x83, 0xD8, 0x00 } |
| static const uint8_t | MUL_RCX [] = { 0x48, 0xf7, 0xe1 } |
| static const uint8_t | REX_SHR_RDX [] = { 0x48, 0xc1, 0xea } |
| static const uint8_t | REX_SH [] = { 0x49, 0xc1 } |
| static const uint8_t | MOV_RCX_RAX_SAR_RCX_63 [] = { 0x48, 0x89, 0xc1, 0x48, 0xc1, 0xf9, 0x3f } |
| static const uint8_t | AND_ECX_I [] = { 0x81, 0xe1 } |
| static const uint8_t | ADD_RAX_RCX [] = { 0x48, 0x01, 0xC8 } |
| static const uint8_t | SAR_RAX_I8 [] = { 0x48, 0xC1, 0xF8 } |
| static const uint8_t | NEG_RAX [] = { 0x48, 0xF7, 0xD8 } |
| static const uint8_t | ADD_R_RAX [] = { 0x4C, 0x03 } |
| static const uint8_t | XOR_EAX_EAX [] = { 0x33, 0xC0 } |
| static const uint8_t | ADD_RDX_R [] = { 0x4c, 0x01 } |
| static const uint8_t | SUB_RDX_R [] = { 0x4c, 0x29 } |
| static const uint8_t | SAR_RDX_I8 [] = { 0x48, 0xC1, 0xFA } |
| static const uint8_t | TEST_RDX_RDX [] = { 0x48, 0x85, 0xD2 } |
| static const uint8_t | SETS_AL_ADD_RDX_RAX [] = { 0x0F, 0x98, 0xC0, 0x48, 0x03, 0xD0 } |
| static const uint8_t | REX_NEG [] = { 0x49, 0xF7 } |
| static const uint8_t | REX_XOR_RR [] = { 0x4D, 0x33 } |
| static const uint8_t | REX_XOR_RI [] = { 0x49, 0x81 } |
| static const uint8_t | REX_XOR_RM [] = { 0x4c, 0x33 } |
| static const uint8_t | REX_ROT_CL [] = { 0x49, 0xd3 } |
| static const uint8_t | REX_ROT_I8 [] = { 0x49, 0xc1 } |
| static const uint8_t | SHUFPD [] = { 0x66, 0x0f, 0xc6 } |
| static const uint8_t | REX_ADDPD [] = { 0x66, 0x41, 0x0f, 0x58 } |
| static const uint8_t | REX_CVTDQ2PD_XMM12 [] = { 0xf3, 0x44, 0x0f, 0xe6, 0x24, 0x06 } |
| static const uint8_t | REX_SUBPD [] = { 0x66, 0x41, 0x0f, 0x5c } |
| static const uint8_t | REX_XORPS [] = { 0x41, 0x0f, 0x57 } |
| static const uint8_t | REX_MULPD [] = { 0x66, 0x41, 0x0f, 0x59 } |
| static const uint8_t | REX_MAXPD [] = { 0x66, 0x41, 0x0f, 0x5f } |
| static const uint8_t | REX_DIVPD [] = { 0x66, 0x41, 0x0f, 0x5e } |
| static const uint8_t | SQRTPD [] = { 0x66, 0x0f, 0x51 } |
| static const uint8_t | AND_OR_MOV_LDMXCSR [] = { 0x25, 0x00, 0x60, 0x00, 0x00, 0x0D, 0xC0, 0x9F, 0x00, 0x00, 0x50, 0x0F, 0xAE, 0x14, 0x24, 0x58 } |
| static const uint8_t | ROL_RAX [] = { 0x48, 0xc1, 0xc0 } |
| static const uint8_t | XOR_ECX_ECX [] = { 0x33, 0xC9 } |
| static const uint8_t | REX_CMP_R32I [] = { 0x41, 0x81 } |
| static const uint8_t | REX_CMP_M32I [] = { 0x81, 0x3c, 0x06 } |
| static const uint8_t | MOVAPD [] = { 0x66, 0x0f, 0x29 } |
| static const uint8_t | REX_MOV_MR [] = { 0x4c, 0x89 } |
| static const uint8_t | REX_XOR_EAX [] = { 0x41, 0x33 } |
| static const uint8_t | SUB_EBX [] = { 0x83, 0xEB, 0x01 } |
| static const uint8_t | JNZ [] = { 0x0f, 0x85 } |
| static const uint8_t | JMP = 0xe9 |
| static const uint8_t | REX_XOR_RAX_R64 [] = { 0x49, 0x33 } |
| static const uint8_t | REX_XCHG [] = { 0x4d, 0x87 } |
| static const uint8_t | REX_ANDPS_XMM12 [] = { 0x45, 0x0F, 0x54, 0xE5, 0x45, 0x0F, 0x56, 0xE6 } |
| static const uint8_t | REX_PADD [] = { 0x66, 0x44, 0x0f } |
| static const uint8_t | PADD_OPCODES [] = { 0xfc, 0xfd, 0xfe, 0xd4 } |
| static const uint8_t | CALL = 0xe8 |
| static const uint8_t | REX_ADD_I [] = { 0x49, 0x81 } |
| static const uint8_t | REX_TEST [] = { 0x49, 0xF7 } |
| static const uint8_t | JZ [] = { 0x0f, 0x84 } |
| static const uint8_t | RET = 0xc3 |
| static const uint8_t | LEA_32 [] = { 0x41, 0x8d } |
| static const uint8_t | MOVNTI [] = { 0x4c, 0x0f, 0xc3 } |
| static const uint8_t | ADD_EBX_I [] = { 0x81, 0xc3 } |
| static const uint8_t | NOP1 [] = { 0x90 } |
| static const uint8_t | NOP2 [] = { 0x66, 0x90 } |
| static const uint8_t | NOP3 [] = { 0x66, 0x66, 0x90 } |
| static const uint8_t | NOP4 [] = { 0x0F, 0x1F, 0x40, 0x00 } |
| static const uint8_t | NOP5 [] = { 0x0F, 0x1F, 0x44, 0x00, 0x00 } |
| static const uint8_t | NOP6 [] = { 0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00 } |
| static const uint8_t | NOP7 [] = { 0x0F, 0x1F, 0x80, 0x00, 0x00, 0x00, 0x00 } |
| static const uint8_t | NOP8 [] = { 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| static const uint8_t * | NOPX [] = { NOP1, NOP2, NOP3, NOP4, NOP5, NOP6, NOP7, NOP8 } |
| const MacroOp | IMULH_R_ops_array [] = { MacroOp::Mov_rr, MacroOp::Mul_r, MacroOp::Mov_rr } |
| const MacroOp | ISMULH_R_ops_array [] = { MacroOp::Mov_rr, MacroOp::Imul_r, MacroOp::Mov_rr } |
| const MacroOp | IMUL_RCP_ops_array [] = { MacroOp::Mov_ri64, MacroOp(MacroOp::Imul_rr, true) } |
| const int | buffer0 [] = { 4, 8, 4 } |
| const int | buffer1 [] = { 7, 3, 3, 3 } |
| const int | buffer2 [] = { 3, 7, 3, 3 } |
| const int | buffer3 [] = { 4, 9, 3 } |
| const int | buffer4 [] = { 4, 4, 4, 4 } |
| const int | buffer5 [] = { 3, 3, 10 } |
| const SuperscalarInstructionInfo * | slot_3 [] = { &SuperscalarInstructionInfo::ISUB_R, &SuperscalarInstructionInfo::IXOR_R } |
| const SuperscalarInstructionInfo * | slot_3L [] = { &SuperscalarInstructionInfo::ISUB_R, &SuperscalarInstructionInfo::IXOR_R, &SuperscalarInstructionInfo::IMULH_R, &SuperscalarInstructionInfo::ISMULH_R } |
| const SuperscalarInstructionInfo * | slot_4 [] = { &SuperscalarInstructionInfo::IROR_C, &SuperscalarInstructionInfo::IADD_RS } |
| const SuperscalarInstructionInfo * | slot_7 [] = { &SuperscalarInstructionInfo::IXOR_C7, &SuperscalarInstructionInfo::IADD_C7 } |
| const SuperscalarInstructionInfo * | slot_8 [] = { &SuperscalarInstructionInfo::IXOR_C8, &SuperscalarInstructionInfo::IADD_C8 } |
| const SuperscalarInstructionInfo * | slot_9 [] = { &SuperscalarInstructionInfo::IXOR_C9, &SuperscalarInstructionInfo::IADD_C9 } |
| const SuperscalarInstructionInfo * | slot_10 = &SuperscalarInstructionInfo::IMUL_RCP |
| constexpr int | CYCLE_MAP_SIZE = RANDOMX_SUPERSCALAR_LATENCY + 4 |
| constexpr int | LOOK_FORWARD_CYCLES = 4 |
| constexpr int | MAX_THROWAWAY_COUNT = 256 |
| static volatile rx_vec_i128 | aesDummy |