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| static bool | randomx::isMultiplication (SuperscalarInstructionType type) |
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| static bool | randomx::selectRegister (std::vector< int > &availableRegisters, Blake2Generator &gen, int ®) |
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| template<bool commit> |
| static int | randomx::scheduleUop (ExecutionPort::type uop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle) |
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| template<bool commit> |
| static int | randomx::scheduleMop (const MacroOp &mop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle, int depCycle) |
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| void | randomx::generateSuperscalar (SuperscalarProgram &prog, Blake2Generator &gen) |
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| void | randomx::executeSuperscalar (int_reg_t(&r)[8], SuperscalarProgram &prog, std::vector< uint64_t > *reciprocals) |
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| constexpr type | randomx::ExecutionPort::Null = 0 |
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| constexpr type | randomx::ExecutionPort::P0 = 1 |
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| constexpr type | randomx::ExecutionPort::P1 = 2 |
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| constexpr type | randomx::ExecutionPort::P5 = 4 |
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| constexpr type | randomx::ExecutionPort::P01 = P0 | P1 |
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| constexpr type | randomx::ExecutionPort::P05 = P0 | P5 |
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| constexpr type | randomx::ExecutionPort::P015 = P0 | P1 | P5 |
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| const MacroOp | randomx::IMULH_R_ops_array [] = { MacroOp::Mov_rr, MacroOp::Mul_r, MacroOp::Mov_rr } |
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| const MacroOp | randomx::ISMULH_R_ops_array [] = { MacroOp::Mov_rr, MacroOp::Imul_r, MacroOp::Mov_rr } |
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| const MacroOp | randomx::IMUL_RCP_ops_array [] = { MacroOp::Mov_ri64, MacroOp(MacroOp::Imul_rr, true) } |
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| const int | randomx::buffer0 [] = { 4, 8, 4 } |
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| const int | randomx::buffer1 [] = { 7, 3, 3, 3 } |
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| const int | randomx::buffer2 [] = { 3, 7, 3, 3 } |
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| const int | randomx::buffer3 [] = { 4, 9, 3 } |
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| const int | randomx::buffer4 [] = { 4, 4, 4, 4 } |
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| const int | randomx::buffer5 [] = { 3, 3, 10 } |
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| const SuperscalarInstructionInfo * | randomx::slot_3 [] = { &SuperscalarInstructionInfo::ISUB_R, &SuperscalarInstructionInfo::IXOR_R } |
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| const SuperscalarInstructionInfo * | randomx::slot_3L [] = { &SuperscalarInstructionInfo::ISUB_R, &SuperscalarInstructionInfo::IXOR_R, &SuperscalarInstructionInfo::IMULH_R, &SuperscalarInstructionInfo::ISMULH_R } |
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| const SuperscalarInstructionInfo * | randomx::slot_4 [] = { &SuperscalarInstructionInfo::IROR_C, &SuperscalarInstructionInfo::IADD_RS } |
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| const SuperscalarInstructionInfo * | randomx::slot_7 [] = { &SuperscalarInstructionInfo::IXOR_C7, &SuperscalarInstructionInfo::IADD_C7 } |
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| const SuperscalarInstructionInfo * | randomx::slot_8 [] = { &SuperscalarInstructionInfo::IXOR_C8, &SuperscalarInstructionInfo::IADD_C8 } |
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| const SuperscalarInstructionInfo * | randomx::slot_9 [] = { &SuperscalarInstructionInfo::IXOR_C9, &SuperscalarInstructionInfo::IADD_C9 } |
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| const SuperscalarInstructionInfo * | randomx::slot_10 = &SuperscalarInstructionInfo::IMUL_RCP |
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| constexpr int | randomx::CYCLE_MAP_SIZE = RANDOMX_SUPERSCALAR_LATENCY + 4 |
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| constexpr int | randomx::LOOK_FORWARD_CYCLES = 4 |
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| constexpr int | randomx::MAX_THROWAWAY_COUNT = 256 |
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