Generate ( 'DpgenConst', modelname
, param = { 'nbit' : n
, 'const' : constVal
, 'physical' : True
, 'behavioral' : True
}
)
n bits constant named modelname.
n bit)
param.
q <= constVal
from stratus import *
class inst_const ( Model ) :
def Interface ( self ) :
self.o = SignalOut ( "o", 32 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenConst', 'const_0x0000ffff'
, param = { 'nbit' : 32
, 'const' : "0x0000FFFF"
, 'physical' : True
}
)
self.I = Inst ( 'const_0x0000ffff', 'inst'
, map = { 'q' : self.o
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref(0, 0) )