Generate ( 'DpgenNbuse', modelname
, param = { 'nbit' : n
, 'physical' : true
, 'behavioral' : true
}
)
n bits tristate with an complemented output named modelname.
n bits )
n bits )
param.
nts:BLOCK(cmd = '1') BEGIN
nq <= GUARDED not(i0);
END
from stratus import *
class inst_nbuse ( Model ) :
def Interface ( self ) :
self.i = SignalIn ( "i", 29 )
self.cmd = SignalIn ( "cmd", 1 )
self.o = SignalOut ( "o", 29 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenNbuse', 'nbuse29'
, param = { 'nbit' : 29
, 'physical' : True
}
)
self.I = Inst ( 'nbuse29', 'inst'
, map = { 'i0' : self.i
, 'cmd' : self.cmd
, 'nq' : self.o
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref(0, 0) )