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#################
D A T A S H E E T
#################


Name             : RM_IHPSG13_2P_64x32_c2
Size             : 64 words x 32 bits
Column Mux       : 2
Number of Ports  : 2
Area (h x w)     : 74.87 x 702.83 = 52620.88 square microns


##################
Introduction
##################


This 2-port macro has a one-cycle data-access.
Both ports operate independly from each other, there is no conflict handling included.
For timing information overview have a look at the timing diagrams in the "Timing Diagrams" section below.

IMPORTANT: Input port A_DLY/B_DLY must always be tied to '1'.


##################
Schematic View
##################


                    ________________________________________
                   |                                        |
                   |                                        |
                ---|A_DIN[31:0]                             |
                ---|A_ADDR[5:0]                             |
                ---|A_MEN                                   |
                ---|A_REN                                   |
                ---|A_WEN                                   |
                ---|A_CLK                                   |
                   |                                        |
                ---|A_DLY                                   |
                   |                                        |
                   |                            A_DOUT[31:0]|---
                   |                                        |
                   |                            B_DOUT[31:0]|---
                   |                                        |
                ---|B_DIN[31:0]                             |
                ---|B_ADDR[5:0]                             |
                ---|B_MEN                                   |
                ---|B_REN                                   |
                ---|B_WEN                                   |
                ---|B_CLK                                   |
                   |                                        |
                ---|B_DLY                                   |
                   |                                        |
                   |________________________________________|


###########################
Macro Interface Signal List
###########################


Signal              Sensitivity                 Logic            Direction     Description
------              -----------                 -----            ---------     -----------
A_ADDR[5:0]         Positive Clock Edge         Positive         Input         6 address bits  
A_DIN[31:0]         Positive Clock Edge         Positive         Input         32 data bits 
A_WEN               Positive Clock Edge         Positive         Input         Write-enable  
A_MEN               Positive Clock Edge         Positive         Input         Memory enable -> if disabled, the memory is deactivated   
A_REN               Positive Clock Edge         Positive         Input         Read enable 
A_CLK               Clock                       Positive         Input         Clock pin   
A_DOUT[31:0]        Positive Clock Edge         Positive         Output        32 data bits, no high impedance function   
A_DLY               Level                       Positive         Input         Delay setting, adjustment of memory internal timings; MANDATORY setting: Tie to 1

B_ADDR[5:0]         Positive Clock Edge         Positive         Input         6 address bits  
B_DIN[31:0]         Positive Clock Edge         Positive         Input         32 data bits 
B_WEN               Positive Clock Edge         Positive         Input         Write-enable  
B_MEN               Positive Clock Edge         Positive         Input         Memory enable -> if disabled, the memory is deactivated   
B_REN               Positive Clock Edge         Positive         Input         Read enable 
B_CLK               Clock                       Positive         Input         Clock pin   
B_DOUT[31:0]        Positive Clock Edge         Positive         Output        32 data bits, no high impedance function   
B_DLY               Level                       Positive         Input         Delay setting, adjustment of memory internal timings; MANDATORY setting: Tie to 1

VDD                                                                            Macro support logic supply voltage
VSS                                                                            Macro support logic ground
VDDARRAY                                                                       Memory array supply voltage
----------------------------------------------------------------------------------------------------------------------------------------------------------




###########################
Operation Tables
###########################



A_MEN         A_REN         A_WEN           Operation on Memory
-----         -----         -----           ----------------------
  0           0 / 1         0 / 1           No Operation
  1             0             0             No Operation
  1             1             0             Read
  1             0             1             Write
  1             1             1             Write-Through



B_MEN         B_REN         B_WEN           Operation on Memory
-----         -----         -----           ----------------------
  0           0 / 1         0 / 1           No Operation
  1             0             0             No Operation
  1             1             0             Read
  1             0             1             Write
  1             1             1             Write-Through




###########################
Timing Diagrams
###########################



                                WRITE                              READ                            WRITE-THROUGH                    NO OPERATION

                                  |-----T_CKH----->|
     ___________                  | ______________ |                 | _______________                   _______________                  _____________
 A_CLK          \                 |/              \|                 |/               \                 /               \                /
                 \_______________/|                |\_______________/|                 \_______________/                 \______________/
                      |           |                                  |                         |
                      |<-Tsetup---|                                  |-------T_CLK2DOUT------->|
     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
 A_ADDR      A_ADDR0 \|/          |          |  A_ADDR1  \/       A_ADDR2                   \/ |        A_ADDR3
     ________________/|\__________|_________ |___________/\_________________________________/\_|_______________________________________________________
                      |           |          |                                                 |
                      |           |---Thold->|                                                 |
     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
 A_DIN               \|/          |          |  A_D1     \/       don't care                \/ |        A_D3
     ________________/|\__________|__________|___________/\_________________________________/\_|_______________________________________________________
                      |           |          |                                                 |
                      | __________|__________|_________________________________________________|______________________
 A_MEN                |/          |          |                                                 |                      \
     ________________/|           |          |                                                 |                       \_______________________________
                      |           |          |                                                 |
                      | __________|_________ |                                               __|______________________
 A_WEN                |/          |         \|                                              /  |                      \
     ________________/|           |          |\____________________________________________/   |                       \_______________________________
                      |           |          |                                                 |
                      |           |          |            _____________________________________|______________________
 A_REN                |           |          |           /                                     |                      \
     _________________|___________|__________|__________/                                      |                       \_______________________________
                      |           |          |                                                 |
     _________________________________________________________________________________________ | ____________________________________  ________________
 A_DOUT                            'X'                                                        \|/         MEMORY(A_ADDR2)            \/    A_D3
     _________________________________________________________________________________________/|\____________________________________/\________________
                                                                                               |
     ________________________________________________  __________________________________________________________________________  ____________________
 A_MEMORY                          'X'               \/          MEMORY(A_ADDR1)=A_D1                                            \/MEMORY(A_ADDR3)=A_D3
     ________________________________________________/\__________________________________________________________________________/\____________________



	

                                WRITE                              READ                            WRITE-THROUGH                    NO OPERATION

                                  |-----T_CKH----->|
     ___________                  | _______________|                 | _______________                   _______________                  _____________
 B_CLK          \                 |/              \|                 |/               \                 /               \                /
                 \_______________/|                |\_______________/|                 \_______________/                 \______________/
                      |           |                                  |                         |
                      |<-Tsetup---|                                  |-------T_CLK2DOUT------->|
     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
 B_ADDR      B_ADDR0 \|/          |          |  B_ADDR1  \/       B_ADDR2                   \/ |        B_ADDR3
     ________________/|\__________|_________ |___________/\_________________________________/\_|_______________________________________________________
                      |           |          |                                                 |
                      |           |---Thold->|                                                 |
     ________________ | __________|__________|___________  _________________________________  _|_______________________________________________________
 B_DIN               \|/          |          |  B_D1     \/       don't care                \/ |        B_D3
     ________________/|\__________|__________|___________/\_________________________________/\_|_______________________________________________________
                      |           |          |                                                 |
                      | __________|__________|_________________________________________________|______________________
 B_MEN                |/          |          |                                                 |                      \
     ________________/|           |          |                                                 |                       \_______________________________
                      |           |          |                                                 |
                      | __________|__________|                                               __|______________________
 B_WEN                |/          |          |\                                             /  |                      \
     ________________/|           |          | \___________________________________________/   |                       \_______________________________
                      |           |          |                                                 |
                      |           |          |            _____________________________________|______________________
 B_REN                |           |          |           /                                     |                      \
     _________________|___________|__________|__________/                                      |                       \_______________________________
                      |           |          |                                                 |
     _________________________________________________________________________________________ | ____________________________________  ________________
 B_DOUT                            'X'                                                        \|/         MEMORY(B_ADDR2)            \/    B_D3
     _________________________________________________________________________________________/|\____________________________________/\________________
                                                                                               |
     ________________________________________________  __________________________________________________________________________  ____________________
 B_MEMORY                          'X'               \/          MEMORY(B_ADDR1)=B_D1                                            \/MEMORY(B_ADDR3)=B_D3
     ________________________________________________/\__________________________________________________________________________/\____________________


	


###########################
Operating Conditions
###########################


+-------------+----------------------+-----------+------+------+-------+
| Symbol      | Parameter            | Condition | Min  | Max  | Units |
+-------------+----------------------+-----------+------+------+-------+
| VDD         | Supply Voltage Range | Operating | 1.08 | 1.32 | V     |
| Temperature |                      | Operating | -55  | 125  | C    |
| tCKH        | Min Pulse Width      | Operating | 0.12 | 0.4  | ns    |
+-------------+----------------------+-----------+------+------+-------+



###########################
Characterization Corners
###########################


+--------------------------+--------------+-----------+-------------+------------------+
| Operating Condition Name | Model Corner | Condition | Voltage [V] | Temperature [C] |
+--------------------------+--------------+-----------+-------------+------------------+
| wc_1d08V_125C            | wc           | working   | 1.08        | 125              |
| bc_1d32V_m55C            | bc           | working   | 1.32        | -55              |
| tc_1d20V_25C             | tc           | working   | 1.20        | 25               |
+--------------------------+--------------+-----------+-------------+------------------+



###########################
Timing Characteristics
###########################


+-------------------+-------------+-----------+---------------+---------------+--------------+-------+
| Timing            | Timing Type | Direction | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units |
+-------------------+-------------+-----------+---------------+---------------+--------------+-------+
| Clock to Data Out | Delay       | Rising    | 5.28e+00      | 1.92e+00      | 3.14e+00     | ns    |
| Clock to Data Out | Delay       | Falling   | 5.16e+00      | 1.88e+00      | 3.07e+00     | ns    |
| Data Out          | Transition  | Rising    | 4.08e-02      | 1.62e-02      | 2.59e-02     | ns    |
| Data Out          | Transition  | Falling   | 3.29e-02      | 1.35e-02      | 2.01e-02     | ns    |
+-------------------+-------------+-----------+---------------+---------------+--------------+-------+



###########################
Power Characteristics
###########################


Typical Power Unit : 1e-12 * J/toggle = 1 * uW/MHz
                            (capacitive_load_unit * voltage_unit^2) per toggle event
------------------------------------------------------------------------------------------
+---------------------+---------------+---------------+--------------+------------+
| Power               | wc_1d08V_125C | bc_1d32V_m55C | tc_1d20V_25C | Units      |
+---------------------+---------------+---------------+--------------+------------+
| Leakage Power       | 2.383e+02     | 1.129e+02     | 3.986e+01    | 1nW        |
| Total Typical Power | 2.439e+01     | 3.764e+01     | 2.957e+01    | 1 * uW/MHz |
+---------------------+---------------+---------------+--------------+------------+



#################
Physical Layout
#################


Metal usage is up to M4. 
The bottom figure shows the physical layout of the 64x32_c2 SRAM hard macro with its dimensions.
Note: Row decoder and interface pin locations as well as location, dimension and number of power rails are approximated.

                                                  702.83 microns
         <-------------------------------------------------------------------------------------------------------->
          _________________________________________________________________________________________________________
       ^ |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  ^
       | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
       | |   |    |   |     |   |     |   |      |        |   |   |        |      |   |    |   |     |   |    |   |  |
       | |PWR|    |ARR|     |PWR|     |ARR|      | L      |PWR|PWR|      R |      |ARR|    |PWR|     |ARR|    |PWR|  |
       | |   |    |AY |     |   |     |AY |      |  E     |   |   |     I  |      | YA|    |   |     | YA|    |   |  |
       | |   |    |   |     |   |     |   |      |   F    |   |   |    G   |      |   |    |   |     |   |    |   |  |
       | |   |    |PWR|     |   |     |PWR|      |    T   |   |   |   H    |      |PWR|    |   |     |PWR|    |   |  |
       | |   |    |   |     |   |     |   |      |        |   |   |  T     |      |   |    |   |     |   |    |   |  |
SRAM   | |   |    |   |     |   |     |   |      |  R     |   |   |     R  |      |   |    |   |     |   |    |   |  |
Array  | |   |    |   |     |   |     |   |      |   O    |   |   |    O   |      |   |    |   |     |   |    |   |  |74.87 microns
       | |S  |    |S  |     |S  |     |S  |      |    W   |S  |  S|   W    |      |  S|    |  S|	 |  S|    |  S|  |
       | | T |    | T |     | T |     | T |      |  D     | T | T |     D  |      | T |    | T |	 | T |    | T |  |
       | |  R|    |  R|     |  R|     |  R|      |   E    |  R|R  |    E   |      |R  |    |R  |	 |R  |    |R  |  |
       | | I |    | I |     | I |     | I |      |    C   | I | I |   C    |      | I |    | I |	 | I |    | I |  |
       | |P  |    |P  |     |P  |     |P  |      |        |P  |  P|        |      |  P|    |  P|	 |  P|    |  P|  |
       | | E |    | E |     | E |     | E |      |        | E | E |        |      | E |    | E |	 | E |    | E |  |
       v |__S|____|__S|_____|__S|_____|__S|______|________|__S|S__|________|______|S__|____|S__|_____|S__|____|S__|  |
       ^ |   |              |   |                |        |   |   |        |               |   |              |   |  |
       | |___|     ___      |___|      ___       |        |___|___|        |       ___     |___|      ___     |___|  |
Inter- | |VDD|    |VDD|     |VDD|     |VDD|      |        |VDD|VDD|        |      |VDD|    |VDD|     |VDD|    |VDD|  |
face   | |VSS|    |VSS|     |VSS|     |VSS|      |        |VSS|VSS|        |      |VSS|    |VSS|     |VSS|    |VSS|  |
Pins   v |___|____|___|_____|___|_____|___|______|________|___|___|________|______|___|____|___|_____|___|____|___|  v




The SRAM macro is physically organized in 2 x 64 horizontal x 64 vertical bit cells:
 - Row address pins (MSB..LSB)     : 4;           ya[3:0]     = ADDR[6:2]         
 - Column address pins (MSB..LSB)  : 2;           xa[1:0]     = ADDR[1:0]         
 - Data pins (MSB..LSB)            : 32;          xa[31:0]    = DIN[31:0], DOUT[31:0].

The scrambling scheme reads as follows:
 - X-Address Scrambling: xa[i] = x[i]
 - Y-Address Scrambling: ya[j] = not(y[j])

Translation from physical (x,y,d) to topological (x,y) addresses:
  x_topo = f(x_physical, y_physical, d) =
                    if (d<12)      {d*32+31-x}    
                    else           {d*32+x}  

  y_topo = f(x_physical, y_physical, d) = y

Note: The left and right sub-arrays are mirrored with respect to the y axis.

Symbol definition:
xa[0..n], ya[0..m]: externally applied device addresses

x[0..n], y[0..m]:   internal physical addresses (address complete memory words)

x_topo, y_topo:     internal topological addresses (address single bit cells)

