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USRP Hardware Driver and USRP Manual
Version: 4.9.0.0-0-unknown
UHD and USRP Manual
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USRP Hardware Driver and USRP Manual
Version: 4.9.0.0-0-unknown
UHD and USRP Manual
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The X4x0 series of USRPs comes in two variants: The USRP X410, and the USRP X440. Both variants share the same enclosure and motherboard, and are collectively referred to as X4x0.
The Ettus USRP X4x0 is a fourth-generation Software Defined Radio (SDR) out of the USRP family of SDRs. Depending on the variant, it contains either two ZBX Daughterboards for a total of 4 channels at up to 400 MHz of analog bandwidth each, or two FBX Daughterboards for a total of 8 channels at up to 1.6 GHz of analog bandwidth. The analog features of the ZBX Daughterboard and the FBX Daughterboard are described in a separate manual page.
The USRP X4x0 features a Xilinx RFSoC, running an embedded Linux system. Like other USRPs, it is addressable through a 1 GbE RJ45 connector, which allows full access to the embedded Linux system, as well as data streaming at low rates. In addition, it features two QSFP28 connectors, which allow for up to 4x10 GbE or 1x100 GbE connections each. The RFSoC used on the USRP X410 is a ZU28DR speed grade 1, on the USRP X440 the ZU28DR speed grade 2.
The front panel provides access to the RF connectors (SMA for X410, MMPX for X440), Tx/Rx status LEDs, programmable GPIOs, and the power button. The rear panel is where the power and data connections go (Ethernet, USB) as well as time/clock reference signals and GPS antenna.
The main chip (the SoC) of the X4x0 is a Xilinx Zynq UltraScale+ RFSoC (ZU28DR). It contains an ARM quad-core Cortex A53 CPU (referred to as the "APU"), an UltraScale+ FPGA including peripherals such as built-in data converters and SD-FEC cores, and an ARM Cortex-R5F real-time processor (the "RPU").
The programmable logic (PL, or FPGA) section of the SoC is responsible for handling all sampling data, the high-speed network connections, and any other high-speed utilities such as custom RFNoC logic. The processing system (PS, or CPU) is running a custom-built OpenEmbedded-based Linux operating system. The OS is responsible for all the device and peripheral management, such as running MPM, configuring the network interfaces, running local UHD sessions, etc.
The programmable logic bitfile contains certain hard-coded configurations of the hardware, such as what type of connectivity the QSFP28 ports use, and how the RF data converters are configured. That means to change the QSFP28 from a 10 GbE to a 100 GbE connection requires changing out the bitfile, as well as when reconfiguring the data converters for different master clock rates. See FPGA Image Flavors for more information.
It is possible to connect to the host OS either via SSH or serial console (see sections SSH Connection and Serial Connection, respectively).
The X4x0 has a higher maximum analog bandwidth than previous USRPs. The USRP X410 can provide rates up to 500 Msps, resulting in a usable analog bandwidth of up to 400 MHz.
The USRP X440 can, depending on the FPGA image used, provide up to 2048 Msps of sampling rate, resulting in a usable analog bandwidth of up to 1.6 GHz on two channels, or 8 channels at 500 Msps.
In order to facilitate the higher bandwidth, UHD may use a technology called Data Plane Development Kit (DPDK). See the DPDK page for details on how it can improve streaming, and how to use it.
The Ettus USRP X410 contains two ZBX daughterboards. To find out more about the capabilities of these analog front-end cards, see ZBX Daughterboard.
The Ettus USRP X440 contains two FBX daughterboards. Unlike the ZBX daughterboards, they have no analog mixers or filters, but directly connect the converters to the RF connectors. To find out more about the capabilities of these analog front-end cards, see FBX Daughterboard.
The X410 front panel provides access to the RF ports and status LEDs of the ZBX Daughterboard. It also provides access to the front-panel GPIO connectors (2x HDMI) and the power button.
The X440 front panel provides access to the RF ports and status LEDs of the FBX Daughterboard. It also provides access to the front-panel GPIO connectors (2x HDMI) and the power button.
The SYNC IN connectors provide access to additional circuitry for advanced time synchronization, in the current version of UHD, they are not supported.
The back panel provides access to power, data connections, clocking and timing related connections, and some status LEDs:
The back panel is identical between X4x0 variants.
The X4x0's cooling system uses a field replaceable fan assembly and supports two variants: one that pulls air front-to-back and one that pulls air back-to-front. By default, the unit comes with the front-to-back fan assembly.
The STM32 microcontroller (also referred to as the "SCU") controls various low-level features of the X4x0 series motherboard: It controls the power sequencing, reads out fan speeds and some of the temperature sensors. It is connected to the RFSoC via an I2C bus. It is running software based on Chromium EC.
It is possible to log into the STM32 using the serial interface (see Connecting to the Microcontroller). This will allow certain low-level controls, such as remote power cycling should the CPU have become unresponsive for whatever reason.
The main non-volatile storage of the USRP is a 16 GB eMMC storage. This storage can be made accessible as a USB Mass Storage device through the USB-OTG connector on the back panel.
The entire root file system (Linux kernel, libraries) and any user data are stored on the eMMC. It is partitioned into four partitions:
Note: It is possible to access the currently inactive root file system by mounting it. After logging into the device using serial console or SSH (see the following two sections), run the following commands:
$ mkdir temp $ mount /dev/mmcblk0p3 temp # This assumes mmcblk0p3 is currently not mounted $ ls temp # You are now accessing the idle partition: bin data etc lib media proc sbin tmp usr boot dev home lost+found mnt run sys uboot var
The device node in the mount command might differ, depending on which partition is currently already mounted.
The USRP X4x0 has two banks of DDR4 memory available for use by the programmable logic in the FPGA. Each bank has a 4 GiB capacity. Because the banks are independent, applications are normally limited to 4 GiB per channel. The DRAM can be run at up to 2.4 GT/s but is clocked at 2.0 GT/s on X410 by default to ease FPGA timing closure.
The FPGA memory controller exposes each bank of DRAM as a 512-bit interface, which is clocked at 300 MHz for X440 and 250 MHz on X410. This interface is then presented to RFNoC as multiple AXI interfaces (one interface for each RF channel). Each AXI interface is sized in order to match the expected throughput for a single channel. For example, on X410 200 MHz images, each AXI interface is 64-bit at 250 MHz. For 400 MHz images, each AXI interface is 128-bit at 250 MHz. This allows for the maximum sample rate to be read and written to DRAM simultaneously.
The default use for the DRAM is the RFNoC Replay block, which supports recording and playback of data in real time. See section FPGA Image Flavors for a list of FPGA images which support the RFNoc Replay block.
The Ettus USRP X4x0 has various network interfaces:
eth0: RJ45 port.sfpX [, sfpX_1, sfpX_2, sfpX_3]: QSFP28 network interface(s), up-to four (one per lane) based on implemented protocol.sfpXfor the first lane, and sfpX_1-3 for the other three lanes. Each network interface has a default static IP address. Note that for multi-lane protocols, such as 100 GbE, a single interface is used (sfpX).int0: internal interface for network communication between the embedded ARM processor and FPGA. It is generally not recommended or necessary to directly connect to this interface.169.254.0.1/24. This interface is agnostic of FPGA image flavor.The configuration files for these network interfaces are stored in: /data/network/<interface>.network.
| Interface Name | Description | Default Configuration | Configuration File | Ex.: X4_xxx FPGA image | Ex.: CG_xxx FPGA image |
|---|---|---|---|---|---|
eth0 | RJ45 | DHCP | eth0.network | DHCP | DHCP |
int0 | Internal | 169.254.0.1/24 | int0.network | 169.254.0.1/24 | 169.254.0.1/24 |
sfp0 | QSFP28 0 (4-lane interface or lane 0) | 192.168.10.2/24 | sfp0.network | 192.168.10.2/24 | 192.168.10.2/24 |
sfp0_1 | QSFP28 0 (lane 1) | 192.168.11.2/24 | sfp0_1.network | 192.168.11.2/24 | N/A |
sfp0_2 | QSFP28 0 (lane 2) | 192.168.12.2/24 | sfp0_2.network | 192.168.12.2/24 | N/A |
sfp0_3 | QSFP28 0 (lane 3) | 192.168.13.2/24 | sfp0_3.network | 192.168.13.2/24 | N/A |
sfp1 | QSFP28 1 (4-lane interface or lane 0) | 192.168.20.2/24 | sfp1.network | N/C | 192.168.20.2/24 |
sfp1_1 | QSFP28 1 (lane 1) | 192.168.21.2/24 | sfp1_1.network | N/C | N/A |
sfp1_2 | QSFP28 1 (lane 2) | 192.168.22.2/24 | sfp1_2.network | N/C | N/A |
sfp1_3 | QSFP28 1 (lane 3) | 192.168.23.2/24 | sfp1_3.network | N/C | N/A |
For FPGA image capability comparison and FPGA naming convention refer to FPGA Image Flavors
For example, /data/network/eth0.network by default looks like:
In order to change the eth0 interface from using DHCP to using a static IP, you can edit /data/network/eth0.network to be like:
replacing the IP address with the IP of your choice.
The Ettus USRP X4x0 is equipped with status LEDs for its network-capable ports: RJ45 and QSFP28s, see RJ45 LED Behavior and QSFP28 LED Behavior accordingly.
The RJ45 port has two independent LEDs: green (right) and yellow (left). The table below summarizes the LEDs' behavior. Note that link speed indication is not currently supported.
| Link / Activity | Green LED | Yellow LED |
|---|---|---|
| No Link | Off | Off |
| Link / No Activity | On | Off |
| Link / Activity | On | Blinking |
Each QSFP28 connector has four LEDs, one for each high-speed transceiver lane. The table below summarizes the LEDs' behavior, note that for multi-lane protocols, such as 100 GbE, the corresponding LEDs are ganged together. Within the same image, multiple speeds on the same port (e.g., both 10 GbE and 100 GbE) are not supported, therefore link speed indication is not supported.
| Link / Activity | QSFP28 LED (4 total) |
|---|---|
| No Link | Off |
| Link / No Activity | Green (solid) |
| Link / Activity | Amber (blinking) |
In this section, users will learn how to set up a device received from the factory to successfully run an application by completing the following steps:
Firstly, download and install UHD on a Linux/OS X/Windows host computer. The easiest way to install USRP Hardware Driver (UHD) is by getting a binary installer package for your operating system as described in Binary Installation. If no binary packages are available for your operating system or you want to modify the sources by yourself, a step-by-step guide is available at Building and Installing UHD from source.
The following minimum UHD versions are required:
It is generally recommended to use the latest UHD version.
1.8.14