rte_pmd_dlb2.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2020 Intel Corporation
 */

#ifndef _RTE_PMD_DLB2_H_
#define _RTE_PMD_DLB2_H_

#include <stdint.h>

#include <rte_compat.h>

#ifdef __cplusplus
extern "C" {
#endif

#define RTE_PMD_DLB2_GET_QID_DEPTH(x) ((x)->rsvd & 0x3)

#define RTE_PMD_DLB2_SET_QID_DEPTH(x, v) ((x)->rsvd = ((x)->rsvd & ~0x3) | (v & 0x3))

#define RTE_PMD_DLB2_GET_QE_WEIGHT(x) (((x)->rsvd >> 2) & 0x3)

#define RTE_PMD_DLB2_SET_QE_WEIGHT(x, v) ((x)->rsvd = ((x)->rsvd & 0x3) | ((v & 0x3) << 2))

enum rte_pmd_dlb2_token_pop_mode {
    /* Pop the CQ tokens immediately after dequeuing. */
    RTE_PMD_DLB2_AUTO_POP,
    /* Pop CQ tokens after (dequeue_depth - 1) events are released.
     * Supported on load-balanced ports only.
     */
    RTE_PMD_DLB2_DELAYED_POP,
    /* Pop the CQ tokens during next dequeue operation. */
    RTE_PMD_DLB2_DEFERRED_POP,

    /* NUM_TOKEN_POP_MODES must be last */
    RTE_PMD_DLB2_NUM_TOKEN_POP_MODES
};

__rte_experimental
int
rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,
                uint8_t port_id,
                enum rte_pmd_dlb2_token_pop_mode mode);

#define DLB2_SET_PORT_FLOW_MIGRATION_THRESHOLD RTE_BIT64(0)

#define DLB2_SET_PORT_HL RTE_BIT64(1)

struct rte_pmd_dlb2_port_param {
    uint16_t inflight_threshold : 12;
    uint16_t port_hl;
};

__rte_experimental
int
rte_pmd_dlb2_set_port_param(uint8_t dev_id,
                uint8_t port_id,
                uint64_t flags,
                struct rte_pmd_dlb2_port_param *val);
#ifdef __cplusplus
}
#endif

#endif /* _RTE_PMD_DLB2_H_ */