#
#	EDAC Kconfig
#	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
#	Licensed and distributed under the GPL

config EDAC_ATOMIC_SCRUB
	bool

config EDAC_SUPPORT
	bool

menuconfig EDAC
	tristate "EDAC (Error Detection And Correction) reporting"
	depends on HAS_IOMEM && EDAC_SUPPORT && RAS
	help
	  EDAC is a subsystem along with hardware-specific drivers designed to
	  report hardware errors. These are low-level errors that are reported
	  in the CPU or supporting chipset or other subsystems:
	  memory errors, cache errors, PCI errors, thermal throttling, etc..
	  If unsure, select 'Y'.

	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.

if EDAC

config EDAC_DEBUG
	bool "Debugging"
	select DEBUG_FS
	help
	  This turns on debugging information for the entire EDAC subsystem.
	  You do so by inserting edac_module with "edac_debug_level=x." Valid
	  levels are 0-4 (from low to high) and by default it is set to 2.
	  Usually you should select 'N' here.

config EDAC_DECODE_MCE
	tristate "Decode MCEs in human-readable form (only on AMD for now)"
	depends on CPU_SUP_AMD && X86_MCE_AMD
	default y
	help
	  Enable this option if you want to decode Machine Check Exceptions
	  occurring on your machine in human-readable form.

	  You should definitely say Y here in case you want to decode MCEs
	  which occur really early upon boot, before the module infrastructure
	  has been initialized.

config EDAC_GHES
	tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
	depends on ACPI_APEI_GHES
	select UEFI_CPER
	help
	  Not all machines support hardware-driven error report. Some of those
	  provide a BIOS-driven error report mechanism via ACPI, using the
	  APEI/GHES driver. By enabling this option, the error reports provided
	  by GHES are sent to userspace via the EDAC API.

	  When this option is enabled, it will disable the hardware-driven
	  mechanisms, if a GHES BIOS is detected, entering into the
	  "Firmware First" mode.

	  It should be noticed that keeping both GHES and a hardware-driven
	  error mechanism won't work well, as BIOS will race with OS, while
	  reading the error registers. So, if you want to not use "Firmware
	  first" GHES error mechanism, you should disable GHES either at
	  compilation time or by passing "ghes.disable=1" Kernel parameter
	  at boot time.

	  In doubt, say 'Y'.

config EDAC_SCRUB
	bool "EDAC scrub feature"
	help
	  The EDAC scrub feature is optional and is designed to control the
	  memory scrubbers in the system. The common sysfs scrub interface
	  abstracts the control of various arbitrary scrubbing functionalities
	  into a unified set of functions.
	  Say 'y/n' to enable/disable EDAC scrub feature.

config EDAC_ECS
	bool "EDAC ECS (Error Check Scrub) feature"
	help
	  The EDAC ECS feature is optional and is designed to control on-die
	  error check scrub (e.g., DDR5 ECS) in the system. The common sysfs
	  ECS interface abstracts the control of various ECS functionalities
	  into a unified set of functions.
	  Say 'y/n' to enable/disable EDAC ECS feature.

config EDAC_MEM_REPAIR
	bool "EDAC memory repair feature"
	help
	  The EDAC memory repair feature is optional and is designed to control
	  the memory devices with repair features, such as Post Package Repair
	  (PPR), memory sparing etc. The common sysfs memory repair interface
	  abstracts the control of various memory repair functionalities into
	  a unified set of functions.
	  Say 'y/n' to enable/disable EDAC memory repair feature.

config EDAC_AMD64
	tristate "AMD64 (Opteron, Athlon64)"
	depends on AMD_NB && EDAC_DECODE_MCE
	depends on AMD_NODE
	imply AMD_ATL
	help
	  Support for error detection and correction of DRAM ECC errors on
	  the AMD64 families (>= K8) of memory controllers.

	  When EDAC_DEBUG is enabled, hardware error injection facilities
	  through sysfs are available:

	  AMD CPUs up to and excluding family 0x17 provide for Memory
	  Error Injection into the ECC detection circuits. The amd64_edac
	  module allows the operator/user to inject Uncorrectable and
	  Correctable errors into DRAM.

	  When enabled, in each of the respective memory controller directories
	  (/sys/devices/system/edac/mc/mcX), there are 3 input files:

	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
	  - inject_word (0..8, 16-bit word of 16-byte section),
	  - inject_ecc_vector (hex ecc vector: select bits of inject word)

	  In addition, there are two control files, inject_read and inject_write,
	  which trigger the DRAM ECC Read and Write respectively.

config EDAC_AL_MC
	tristate "Amazon's Annapurna Lab Memory Controller"
	depends on (ARCH_ALPINE || COMPILE_TEST)
	help
	  Support for error detection and correction for Amazon's Annapurna
	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.

config EDAC_AMD76X
	tristate "AMD 76x (760, 762, 768)"
	depends on PCI && X86_32
	help
	  Support for error detection and correction on the AMD 76x
	  series of chipsets used with the Athlon processor.

config EDAC_E7XXX
	tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
	depends on PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  E7205, E7500, E7501 and E7505 server chipsets.

config EDAC_E752X
	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
	depends on PCI && X86
	help
	  Support for error detection and correction on the Intel
	  E7520, E7525, E7320 server chipsets.

config EDAC_I82875P
	tristate "Intel 82875p (D82875P, E7210)"
	depends on PCI && X86_32
	help
	  Support for error detection and correction on the Intel
	  DP82785P and E7210 server chipsets.

config EDAC_I82975X
	tristate "Intel 82975x (D82975x)"
	depends on PCI && X86
	help
	  Support for error detection and correction on the Intel
	  DP82975x server chipsets.

config EDAC_I3000
	t