[oc] piplelined Radix 16 modular multiplier

["Umair Farooq Siddiqi" <e.engineer@ieee.org>]

Hi

 

I am Undergraduate student of EE.

 

I have designed a piplined radix 16 modular multiplier in VHDL.  

 

The deisgn is RISC based with RAM based Look Up Table. I am trying to design a reconfigurable LUT for Xilinx FPGA implementation.  

 

I will welcome all responses and anyone help me in putting it here and work with me in improve this design. I donot know the exact procedure for putting designs here but i read in the FAQ that it's for everyone.

 

Thanks

 

Umair