head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2005.04.23.00.41.01; author tak.sugawara; state Exp; branches 1.1.1.1; next ; commitid 1113426998c94567; 1.1.1.1 date 2005.04.23.00.41.01; author tak.sugawara; state Exp; branches; next ; commitid 1113426998c94567; desc @@ 1.1 log @Initial revision @ text @Release 7.1i par H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ATHRON:: Wed Apr 13 22:25:08 2005 par -w -intstyle ise -ol std -t 1 s3_vsmpl_map.ncd s3_vsmpl.ncd s3_vsmpl.pcf Constraints file: s3_vsmpl.pcf. Loading device for application Rf_Device from file '3s200.nph' in environment E:/Xilinx7.1. "s3_vsmpl" is an NCD, version 3.1, device xc3s200, package ft256, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.35 2005-01-22". Device Utilization Summary: Number of BUFGMUXs 2 out of 8 25% Number of External IOBs 103 out of 173 59% Number of LOCed IOBs 103 out of 103 100% Number of MULT18X18s 2 out of 12 16% Number of RAMB16s 11 out of 12 91% Number of Slices 1918 out of 1920 99% Number of SLICEMs 1 out of 960 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) WARNING:Par:276 - The signal button<0>_IBUF has no load WARNING:Par:276 - The signal button<1>_IBUF has no load WARNING:Par:276 - The signal button<2>_IBUF has no load WARNING:Par:276 - The signal PS2_DATA_IBUF has no load WARNING:Par:276 - The signal PS2_CLK_IBUF has no load Starting Placer Phase 1.1 Phase 1.1 (Checksum:99018f) REAL time: 5 secs Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs Phase 3.2 . Phase 3.2 (Checksum:1c9c37d) REAL time: 6 secs Phase 4.8 .................................................. Phase 4.8 (Checksum:1108dd3) REAL time: 20 secs Phase 5.5 Phase 5.5 (Checksum:2faf07b) REAL time: 21 secs Phase 6.18 Phase 6.18 (Checksum:39386fa) REAL time: 29 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 29 secs Writing design to file s3_vsmpl.ncd Total REAL time to Placer completion: 31 secs Total CPU time to Placer completion: 24 secs Starting Router Phase 1: 13709 unrouted; REAL time: 31 secs Phase 2: 12745 unrouted; REAL time: 32 secs Phase 3: 11145 unrouted; REAL time: 36 secs Phase 4: 0 unrouted; REAL time: 3 mins 13 secs WARNING:CLK Net:clk25M<0> may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. Total REAL time to Router completion: 3 mins 13 secs Total CPU time to Router completion: 2 mins 57 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk25M<0> | BUFGMUX7| No | 804 | 0.041 | 1.052 | +---------------------+--------------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX0| No | 3 | 0.040 | 1.050 | +---------------------+--------------+------+------+------------+-------------+ INFO:Par:340 - The Delay report will not be generated when running non-timing driven PAR with effort level Standard or Medium. If a delay report is required please do one of the following: 1) use effort level High, 2) use the following environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing constraints for the design. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 3 mins 18 secs Total CPU time to PAR completion: 3 mins Peak Memory Usage: 104 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 5 Number of info messages: 1 Writing design to file s3_vsmpl.ncd PAR done! @ 1.1.1.1 log @no message @ text @@