head	1.2;
access;
symbols
	arelease:1.1.1.1 avendor:1.1.1;
locks; strict;
comment	@# @;


1.2
date	2004.06.24.12.31.11;	author unneback;	state Exp;
branches;
next	1.1;

1.1
date	2004.04.30.15.01.14;	author unneback;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2004.04.30.15.01.14;	author unneback;	state Exp;
branches;
next	;


desc
@@


1.2
log
@corrected generation of err_i and rty_i signals for cbs systems
@
text
@# Generated by PERL program wishbone.pl.
# File used as input for wishbone arbiter generation
# Generated Thu Jun 24 14:29:34 2004

filename=wb
intercon=intercon
syscon=syscon
target=altera
hdl=vhdl
signal_groups=1
tga_bits=2
tgc_bits=3
tgd_bits=0
rename_tga=bte
rename_tgc=cti
rename_tgd=tgd
classic=000
endofburst=111
dat_size=32
adr_size=32
mux_type=andor
interconnect=crossbarswitch

master or32_i
  type=ro
  lock_o=0
  tga_o=1
  tgc_o=1
  tgd_o=0
  err_i=1
  rty_i=1
  priority_uart=0
  priority_sdram_ctrl1=3
  priority_sdram_ctrl2=1
  priority_bootRAM=1
  priority_ethernets=0
end master or32_i

master or32_d
  type=rw
  lock_o=0
  tga_o=1
  tgc_o=1
  tgd_o=0
  err_i=1
  rty_i=1
  priority_uart=1
  priority_sdram_ctrl1=1
  priority_sdram_ctrl2=3
  priority_bootRAM=1
  priority_ethernets=1
end master or32_d

master debug
  type=rw
  lock_o=0
  tga_o=0
  tgc_o=0
  tgd_o=0
  err_i=1
  rty_i=1
  priority_uart=0
  priority_sdram_ctrl1=1
  priority_sdram_ctrl2=1
  priority_bootRAM=1
  priority_ethernets=0
end master debug

master ethernetm
  type=rw
  lock_o=0
  tga_o=1
  tgc_o=1
  tgd_o=0
  err_i=1
  rty_i=0
  priority_uart=0
  priority_sdram_ctrl1=1
  priority_sdram_ctrl2=1
  priority_bootRAM=0
  priority_ethernets=0
end master ethernetm

slave uart
  type=rw
  adr_i_hi=4
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x90000000
  size=0x01000000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave uart

slave sdram_ctrl1
  type=rw
  adr_i_hi=23
  adr_i_lo=2
  tga_i=0
  tgc_i=1
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x00000000
  size=0x10000000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave sdram_ctrl1

slave sdram_ctrl2
  type=rw
  adr_i_hi=23
  adr_i_lo=2
  tga_i=0
  tgc_i=1
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x10000000
  size=0x10000000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave sdram_ctrl2

slave bootRAM
  type=ro
  adr_i_hi=11
  adr_i_lo=2
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0xf0000000
  size=0x10000000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave bootRAM

slave ethernets
  type=rw
  adr_i_hi=11
  adr_i_lo=2
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=1
  rty_o=0
  baseadr=0x92000000
  size=0x01000000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave ethernets
@


1.1
log
@Initial revision
@
text
@d3 1
a3 1
# Generated Fri Apr 30 16:20:22 2004
d33 4
a36 1
  priority_bootRAM=3
d48 2
d51 1
d54 30
d95 1
a95 1
  size=0x00100000
d102 36
d139 1
a139 1
  type=rw
d148 2
a149 2
  baseadr=0x00000000
  size=0x00100000
d155 18
@


1.1.1.1
log
@Initial check-in
@
text
@@