head	1.3;
access;
symbols
	rel_19:1.3
	rel_1:1.1;
locks; strict;
comment	@# @;


1.3
date	2003.09.23.13.09.26;	author markom;	state Exp;
branches;
next	1.2;

1.2
date	2003.03.19.17.27.37;	author rherveille;	state Exp;
branches;
next	1.1;

1.1
date	2001.08.21.05.42.33;	author rudi;	state Exp;
branches;
next	;


desc
@@


1.3
log
@all WB outputs are registered, but just when we dont use cursors
@
text
@
all:	sim
SHELL = /bin/sh
#MS="-s"

##########################################################################
#
# DUT Sources
#
##########################################################################
DUT_SRC_DIR=../../../rtl/verilog
_TARGETS_=	$(DUT_SRC_DIR)/generic_dpram.v		\
		$(DUT_SRC_DIR)/generic_spram.v		\
		$(DUT_SRC_DIR)/csm_spram_bw.v		\
		$(DUT_SRC_DIR)/vga_colproc.v		\
		$(DUT_SRC_DIR)/vga_csm_pb.v		\
		$(DUT_SRC_DIR)/vga_cur_cregs.v		\
		$(DUT_SRC_DIR)/vga_curproc.v		\
		$(DUT_SRC_DIR)/vga_enh_top.v 		\
		$(DUT_SRC_DIR)/vga_dvi_top.v 		\
		$(DUT_SRC_DIR)/vga_fifo.v		\
		$(DUT_SRC_DIR)/vga_fifo_dc.v		\
		$(DUT_SRC_DIR)/vga_pgen.v		\
		$(DUT_SRC_DIR)/vga_tgen.v		\
		$(DUT_SRC_DIR)/vga_vtim.v		\
		$(DUT_SRC_DIR)/vga_wb_master.v		\
		$(DUT_SRC_DIR)/vga_wb_slave.v


##########################################################################
#
# Test Bench Sources
#
##########################################################################
TB_SRC_DIR=../../../bench/verilog
_TB_=		$(TB_SRC_DIR)/test_bench_top.v		\
		$(TB_SRC_DIR)/wb_slv_model.v		\
		$(TB_SRC_DIR)/wb_mast_model.v		\
		$(TB_SRC_DIR)/sync_check.v		\
		$(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw_bist.v	\
		$(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24_bist.v	\
		$(TB_SRC_DIR)/bist/rtl/verilog/bist_dp_top.v        \
		$(TB_SRC_DIR)/bist/rtl/verilog/bist_sp_top.v        \
		$(TB_SRC_DIR)/bist/rtl/verilog/bist_tp_top.v        \
		$(TB_SRC_DIR)/bist/rtl/verilog/bist.v               \
		$(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw/art_hssp_512x24_bw.v	\
		$(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24/art_hsdp_128x24.v	\
		$(TB_SRC_DIR)/wb_b3_check.v

##########################################################################
#
# Misc Variables
#
##########################################################################

_TOP_=test
INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
LOGF=-LOGFILE .nclog
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
GATE_NETLIST=../../../syn/out/vga_vga_and_clut_ps.v

##########################################################################
#
# Make Targets
#
##########################################################################
simw:
	@@$(MAKE) -s sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"

ss:
	signalscan -do waves/waves.do -waves waves/waves.trn &

sim:
	@@echo ""
	@@echo "----- Running NCVLOG ... ----------"
	@@$(MAKE) $(MS) vlog				\
		TARGETS="$(_TARGETS_)"			\
		TB="$(_TB_)"				\
		INCDIR=$(INCDIR)			\
		WAVES="$(WAVES)"			\
		TOP=$(_TOP_)
	@@echo ""
	@@echo "----- Running NCELAB ... ----------"
	@@$(MAKE) $(MS) elab				\
		ACCESS="$(ACCESS)" TOP=$(_TOP_)
	@@echo ""
	@@echo "----- Running NCSIM ... ----------"
	@@$(MAKE) $(MS) ncsim				\
		TOP=$(_TOP_)
	@@echo ""


gatew:
	@@$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"

gate:
	@@echo ""
	@@echo "----- Running NCVLOG ... ----------"
	$(MAKE)$(MS) vlog				\
		TARGETS="$(UMC_LIB) $(GATE_NETLIST)"	\
		TB="$(_TB_)"				\
		INCDIR=$(INCDIR)			\
		WAVES="$(WAVES)"
	@@echo ""
	@@echo "----- Running NCELAB ... ----------"
	@@$(MAKE) $(MS) elab				\
		ACCESS="$(ACCESS)" TOP=$(_TOP_)
	@@echo ""
	@@echo "----- Running NCSIM ... ----------"
	@@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
	@@echo ""


hal:
	@@echo ""
	@@echo "----- Running HAL ... ----------"
	hal	+incdir+$(DUT_SRC_DIR)                          \
		-NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK  \
		"$(_TARGETS_)"
	@@echo "----- DONE ... ----------"

clean:
	rm -rf	./waves/*.dsn ./waves/*.trn	\
		ncwork/worklib/* ncwork/count/*	\
		ncwork/worklib/.i* ncwork/count/.i* 

##########################################################################
#
# NCVLOG
#
##########################################################################

vlog:
	ncvlog $(NCCOMMON) $(LOGF) 				\
		-WORK worklib $(WAVES) $(TARGETS) $(TB) $(INCDIR)

##########################################################################
#
# NCELAB
#
##########################################################################

elab:
	ncelab	$(NCCOMMON) $(LOGF) -APPEND_LOG 		\
		-WORK worklib $(ACCESS) 				\
		-NOTIMINGCHECKS        \
		worklib.$(TOP)

##########################################################################
#
# NCSIM
#
##########################################################################

ncsim:
	ncsim	$(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-EXIT -ERRORMAX 10 worklib.$(TOP)



@


1.2
log
@Added wb_b3_check
Removed ud_cnt, ro_cnt
@
text
@d14 1
d20 1
d40 8
a49 1

d125 2
a126 2
		ncwork/work/* ncwork/count/*	\
		ncwork/work/.i* ncwork/count/.i* 
d136 1
a136 1
		-WORK work $(WAVES) $(TARGETS) $(TB) $(INCDIR)
d146 3
a148 2
		-WORK work $(ACCESS) 				\
		work.$(TOP)
d158 1
a158 1
		-EXIT -ERRORMAX 10 work.$(TOP)
@


1.1
log
@
- Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements
@
text
@d12 3
a14 4
_TARGETS_=	$(DUT_SRC_DIR)/ro_cnt.v			\
		$(DUT_SRC_DIR)/ud_cnt.v			\
		$(DUT_SRC_DIR)/vga_vga_and_clut.v	\
		$(DUT_SRC_DIR)/vga_top.v		\
d16 4
a20 2
		$(DUT_SRC_DIR)/vga_fifo.v		\
		$(DUT_SRC_DIR)/vga_vtim.v		\
a21 1
		$(DUT_SRC_DIR)/vga_colproc.v		\
d23 1
d34 1
a34 1
_TB_="		$(TB_SRC_DIR)/test_bench_top.v		\
d38 2
a39 2
		$(DUT_SRC_DIR)/vga_dpm.v		\
		"
d70 1
a70 1
		TB=$(_TB_)				\
d73 1
a73 1
		TOP=test
d81 1
a81 1
		TOP=test
d93 1
a93 1
		TB=$(_TB_)				\
d111 1
a111 1
		$(_TARGETS_)
a124 6
vhdl:
	ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-WORK count -V93 $(DUT_SRC_DIR)/counter.vhd
	ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-WORK work -V93 $(TARGETS)

d149 1
@