head	1.1;
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comment	@:: @;


1.1
date	2008.08.25.00.39.39;	author sfielding;	state Exp;
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commitid	118148b1fdaa4567;


desc
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1.1
log
@usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project
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@copy /Y ..\..\RTL\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\buffers\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\busInterface\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\hostSlaveMux\hostSlaveMuxBI.v.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\include\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\serialInterfaceEngine\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\slaveController\*.v usbDeviceActelTop\hdl
copy /Y ..\..\..\RTL\wrapper\usbSlave.v usbDeviceActelTop\hdl

pause

@