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1.6
date	2001.08.12.18.41.09;	author gorban;	state dead;
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1.5
date	2001.06.23.11.21.33;	author gorban;	state Exp;
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1.4
date	2001.06.02.14.28.13;	author gorban;	state Exp;
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1.3
date	2001.05.31.20.08.01;	author gorban;	state Exp;
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1.2
date	2001.05.29.20.05.04;	author gorban;	state Exp;
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1.1
date	2001.05.27.17.37.47;	author gorban;	state Exp;
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desc
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1.6
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@remove old directories
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@Note: This Changes file is being maintained since 25.5.2001.

23.06.2001
~~~~~~~~~~

* With the help of Bob Kirstein another two bugs were fixed:
   1. Trasmitter was sending stop bit two 16xclock cycle slonger than needed.
   2. Receiver was losing 1 16xclock cycle on each character and went out of sync.

* Major change: 
    I have modified the divisor latch register to be 16-bit long instead of 32 as I thought was
    necessary for higher speed systems. Thanks to Rick Wright for pointing this out.
    So now, DL3 and DL4 register bytes are not used.
    Documentation is updated to follow this change.

* Note that more than 1 stop bit in a byte i snot implemented.

2.05.2001
~~~~~~~~~

* Fixed transmitter and receiver - the start and the stop bits were sent and received complemented.
  Big thanks go to Bob Kirstein for pointing this out to me.


31.05.2001
~~~~~~~~~~

* Minor changes in register reading code
* Changed FCR to be 2 bits wide (reset bits are not needed) and instead enabled the rx_reset and tx_reset
   signals which I forgot to implement.
* Changed defines for FCR.
* Cleaned ports that were not connected in top-level.
* Changed the code to have only one FIFO module instead of two to overcome versioning problem on the cost of
   some additional gate count. UART_RX_FIFO was modified a little and renamed to UART_FIFO.
* UART_RX_FIFO.v and UART_TX_FIFO.v files removed from the project.
* Changes to receiver and transmitter modules concerning FIFO handling.
* Commented out `include "UART_defines" in all files but UART_top.v and test bench.
* Modified test bench a little for a little better check.


29.05.2001
~~~~~~~~~~

* Fixed: Line Control Register block didn't have wb_rst_i in its sensitivity list
* Fixed: Modem Status Register block didn't have wb_rst_i in its sensitivity list and didn't set reset value
* Fixed rf_pop, lsr_mask, msi_reset and threi_clear not being synthesizable in release 1.7. (Thanks 
	to Pavel Korenski for pointing this to me)


27.05.2001
~~~~~~~~~~

Thanks to Rick Wright for pointing me many of my bugs.

* Fixed the rf_pop and lsr_mask flags not being deasserted.
* Fixed Time-Out interrupt not being masked by bit 0 in IER
* Fixed interrupt logic not being masked by IER
* Fixed bit 0 (interrupt pending) of IIR being set incorrectly
* Fixed Modem Status Register bits 3:0 handling (didn't work as should have)
* Fixed modem status interrupt to be related to bits [3:0] (deltas) instead of the bits 7:4 of MSR.
   This way the interrupt is cleared upon reading from the MSR.
* Fixed THRE interrupt not being reset by reading IIR
* Changed Receiver and Transmitter FIFO, so that they do not use the FIFO_inc.v file because of problems
  with #include command.
* Removed FIFO_inc.v from CVS tree.

* Updated specifications .pdf file

@


1.5
log
@DL made 16-bit long. Fixed transmission/reception bugs.
@
text
@@


1.4
log
@Fixed receiver and transmitter. Major bug fixed.
@
text
@d3 15
@


1.3
log
@FIFO changes and other corrections.
@
text
@d3 7
@


1.2
log
@Fixed some bugs and synthesis problems.
@
text
@d3 26
a28 1
27.05.2001 (release 1.7)
a45 8

29.05.2001 (release 1.8)
~~~~~~~~~~

* Fixed: Line Control Register block didn't have wb_rst_i in its sensitivity list
* Fixed: Modem Status Register block didn't have wb_rst_i in its sensitivity list and didn't set reset value
* Fixed rf_pop, lsr_mask, msi_reset and threi_clear not being synthesizable in release 1.7. (Thanks 
	to Pavel Korenski for pointing this to me)
@


1.1
log
@Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
@
text
@d3 1
a3 1
27.05.2001
d6 2
d21 8
@