head	1.2;
access;
symbols
	rel_1_1:1.2
	rel_1_0:1.2
	rel_0_6_1_beta:1.2
	rel_0_6__beta:1.2
	rel_0_6_beta:1.2
	rel_0_5_beta:1.2
	rel_0_4_beta:1.2
	rel_0_3_beta:1.2
	rel_0_2_beta:1.2
	rel_0_1_beta:1.1.1.1
	transfer:1.1.1.1
	local:1.1.1;
locks; strict;
comment	@;; @;


1.2
date	2004.05.17.14.42.09;	author arniml;	state Exp;
branches;
next	1.1;

1.1
date	2004.03.25.22.29.18;	author arniml;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2004.03.25.22.29.18;	author arniml;	state Exp;
branches;
next	;


desc
@@


1.2
log
@update for changes in address space of external memory
@
text
@	;; *******************************************************************
	;; $Id: test.asm,v 1.1.1.1 2004/03/25 22:29:18 arniml Exp $
	;;
	;; Test MOVX A, @@ Rr for RB0.
	;; *******************************************************************

	INCLUDE	"cpu.inc"
	INCLUDE	"pass_fail.inc"

	ORG	0

	;; Start of test
	mov	r0, #0FEH
fill_loop1:
	mov	a, r0
	movx	@@r0, a
	djnz	r0, fill_loop1

	;; check memory
	mov	a, r0
	jnz	fail
	mov	r0, #0FEH
	mov	r1, #002H
check_loop1:
	clr	a
	movx	a, @@r1
	add	a, r0
	jnz	fail
	inc	r1
	dec	r0
	mov	a, r0
	dec	a
	jnz	check_loop1



	mov	r1, #0FEH
	mov	a, #002H
fill_loop2:
	movx	@@r1, a
	inc	a
	djnz	r1, fill_loop2

	;; check memory
	mov	a, r1
	jnz	fail
	mov	r0, #0FEH
check_loop2:
	clr	a
	movx	a, @@r0
	add	a, r0
	jnz	fail
	dec	r0
	mov	a, r0
	dec	a
	jnz	check_loop2

pass:	PASS

fail:	FAIL
@


1.1
log
@Initial revision
@
text
@d2 1
a2 1
	;; $Id: test.asm,v 1.1 2004/03/16 23:55:40 arnim Exp $
d13 1
a13 1
	mov	r0, #0FFH
d22 2
a23 2
	mov	r0, #0FFH
	mov	r1, #001H
d25 1
d29 1
d31 2
a32 2
	inc	r1
	mov	a, r1
d37 2
a38 2
	mov	r1, #0FFH
	mov	a, #001H
d45 1
a45 1
	mov	a, r0
d47 1
a47 1
	mov	r0, #0FFH
d49 1
d53 4
a56 1
	djnz	r0, check_loop2
@


1.1.1.1
log
@Imported sources
@
text
@@