head	1.2;
access;
symbols
	rel_0_6_1_beta:1.1
	rel_0_6__beta:1.1
	rel_0_6_beta:1.1
	rel_0_5_beta:1.1
	rel_0_4_beta:1.1
	rel_0_3_beta:1.1
	rel_0_2_beta:1.1
	rel_0_1_beta:1.1;
locks; strict;
comment	@# @;


1.2
date	2006.06.21.01.10.25;	author arniml;	state dead;
branches;
next	1.1;
commitid	5d7e44989c764567;

1.1
date	2004.03.24.21.32.27;	author arniml;	state Exp;
branches;
next	;


desc
@@


1.2
log
@obsoleted by new memory concept
@
text
@-------------------------------------------------------------------------------
--
-- A synchronous parametrizable ROM.
--
-- $Id: syn_rom-e.vhd,v 1.1 2004/03/24 21:32:27 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
--      http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity syn_rom is

  generic (
    address_width_g : positive := 10
  );
  port (
    clk_i      : in  std_logic;
    rom_addr_i : in  std_logic_vector(address_width_g-1 downto 0);
    rom_data_o : out std_logic_vector(7 downto 0)
  );

end syn_rom;
@


1.1
log
@initial check-in
@
text
@d5 1
a5 1
-- $Id: syn_rom-e.vhd,v 1.1 2004/03/20 15:27:51 arnim Exp $
@