head	1.2;
access;
symbols
	rel_1_1:1.2
	rel_1_0:1.2
	rel_0_1_beta:1.2;
locks; strict;
comment	@;; @;


1.2
date	2006.05.24.00.48.04;	author arniml;	state Exp;
branches;
next	1.1;
commitid	10564473ad344567;

1.1
date	2006.05.23.01.11.13;	author arniml;	state Exp;
branches;
next	;
commitid	45b24472612f4567;


desc
@@


1.2
log
@check CKO in general purpose configuration
@
text
@	;; *******************************************************************
	;; $Id: test.asm,v 1.1 2006/05/23 01:11:13 arniml Exp $
	;;
	;; Checks the INIL instruction.
	;;

	;; the cpu type is defined on asl's command line

	org	0x00
	clra

	;; check reset level of latches
	inil
	x	0
	skmbz	3
	jmp	fail
	skmbz	2		; CKO
	jmp	fail
	skmbz	0
	jmp	fail


	;; set IN to 0xf and recheck levels
	ogi	0xf
	nop
	nop
	inil
	x	0
	skmbz	3
	jmp	fail
	skmbz	2		; CKO
	jp	+
	jmp	fail
+	skmbz	0
	jmp	fail


	;; set IN0 to 0 and check that IL0 triggered
	ogi	0xe
	nop
	inil
	x	0
	skmbz	3
	jmp	fail
	skmbz	2		; CKO
	jp	+
	jmp	fail
+	skmbz	0
	jp	+
	jmp	fail
+

	jmp	page_1
	org	0x040
page_1:

	;; set IN3 to 0 and check that IL1 triggered
	ogi	0x6
	nop
	inil
	x	0
	skmbz	3
	jp	+
	jmp	fail
+	skmbz	2		; CKO
	jp	+
	jmp	fail
+	skmbz	0
	jmp	fail


	;; reload IN3 to trigger both IL latches
	ogi	0x9
	ogi	0x0
	nop
	inil
	x	0
	skmbz	3
	jp	+
	jmp	fail
+	skmbz	2		; CKO
	jmp	fail
	skmbz	0
	jp	+
	jmp	fail
+


	;; check that INIL prevents setting of IL latches
	;; when both events occur at the same cycle
	ogi	0x9
	ogi	0x0
	inil
	x	0
	skmbz	3
	jmp	fail
	skmbz	2		; CKO
	jmp	fail
	skmbz	0
	jmp	fail


	jmp	pass


	org	0x100	
	include	"pass_fail.asm"
@


1.1
log
@initial check-in
@
text
@d2 1
a2 1
	;; $Id$
d17 2
d31 4
a34 1
	skmbz	0
d45 4
a48 1
	skmbz	0
d53 3
d65 3
a71 3
	jmp	page_1
	org	0x040
page_1:
d81 3
a83 1
+	skmbz	0
d97 2
@