head	1.3;
access;
symbols
	rel_1_1:1.3
	rel_1_0:1.3
	rel_0_1_beta:1.3;
locks; strict;
comment	@# @;


1.3
date	2006.05.27.19.09.29;	author arniml;	state Exp;
branches;
next	1.2;
commitid	5344478a3dd4567;

1.2
date	2006.05.23.01.17.25;	author arniml;	state Exp;
branches;
next	1.1;
commitid	493d4472629c4567;

1.1
date	2006.05.15.21.55.27;	author arniml;	state Exp;
branches;
next	;
commitid	732b4468f8cc4567;


desc
@@


1.3
log
@add global signals for testbench instrumentation
@
text
@-------------------------------------------------------------------------------
--
-- $Id: tb_pack-p.vhd,v 1.2 2006/05/23 01:17:25 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

use work.t400_pack.pc_t;

package tb_pack is

  component tb_elems
    generic (
      period_g  : time := 4.75 us;
      d_width_g : integer := 4;
      g_width_g : integer := 4
    );
    port (
      io_l_i  : in  std_logic_vector(7 downto 0);
      io_d_i  : in  std_logic_vector(d_width_g-1 downto 0);
      io_g_i  : in  std_logic_vector(g_width_g-1 downto 0);
      io_in_o : out std_logic_vector(g_width_g-1 downto 0);
      so_i    : in  std_logic;
      si_o    : out std_logic;
      sk_i    : in  std_logic;
      ck_o    : out std_logic
    );
  end component;

  signal tb_pc_s : pc_t;
  signal tb_sa_s : pc_t;

end tb_pack;


-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb_pack-p.vhd,v $
-- Revision 1.2  2006/05/23 01:17:25  arniml
-- drive IN port
--
-- Revision 1.1  2006/05/15 21:55:27  arniml
-- initial check-in
--
-------------------------------------------------------------------------------
@


1.2
log
@drive IN port
@
text
@d3 1
a3 1
-- $Id: tb_pack-p.vhd,v 1.1 2006/05/15 21:55:27 arniml Exp $
d14 2
d36 3
d46 3
@


1.1
log
@initial check-in
@
text
@d3 1
a3 1
-- $Id$
d23 8
a30 7
      io_l_i : in  std_logic_vector(7 downto 0);
      io_d_i : in  std_logic_vector(d_width_g-1 downto 0);
      io_g_i : in  std_logic_vector(g_width_g-1 downto 0);
      so_i   : in  std_logic;
      si_o   : out std_logic;
      sk_i   : in  std_logic;
      ck_o   : out std_logic
d40 4
a43 1
-- $Log$
@