head	1.2;
access;
symbols
	rel_1_1:1.2
	rel_1_0:1.2
	rel_0_1_beta:1.2;
locks; strict;
comment	@# @;


1.2
date	2006.06.05.14.42.50;	author arniml;	state Exp;
branches;
next	1.1;
commitid	125b448442e64567;

1.1
date	2006.05.27.19.08.21;	author arniml;	state Exp;
branches;
next	;
commitid	44f4478a3a44567;


desc
@@


1.2
log
@fix typo
@
text
@-------------------------------------------------------------------------------
--
-- Testbench for interrupt evaluation.
--
-- $Id: tb_int-c.vhd,v 1.1 2006/05/27 19:08:21 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------

configuration tb_int_behav_c0 of tb_int is

  for behav

    for t420_b: t420
      use configuration work.t420_struct_c0;
    end for;

    for tb_elems_b: tb_elems
      use configuration work.tb_elems_behav_c0;
    end for;

  end for;

end tb_int_behav_c0;


-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb_int-c.vhd,v $
-- Revision 1.1  2006/05/27 19:08:21  arniml
-- initial check-in
--
-------------------------------------------------------------------------------
@


1.1
log
@initial check-in
@
text
@d3 1
a3 1
-- Testbench for interupt evaluation.
d5 1
a5 1
-- $Id$
d33 4
a36 1
-- $Log$
@