head	1.4;
access;
symbols;
locks; strict;
comment	@# @;


1.4
date	2007.11.10.13.58.09;	author fafa1971;	state Exp;
branches;
next	1.3;
commitid	655a4735b8db4567;

1.3
date	2007.10.26.21.52.49;	author fafa1971;	state Exp;
branches;
next	1.2;
commitid	7ee1472261a04567;

1.2
date	2007.10.24.21.45.15;	author fafa1971;	state Exp;
branches;
next	1.1;
commitid	1765471fbcdb4567;

1.1
date	2007.10.24.21.37.28;	author fafa1971;	state Exp;
branches;
next	;
commitid	121e471fbaed4567;


desc
@@


1.4
log
@New version of scripts for DC and to compile boot code
@
text
@set search_path [concat [list ~] $search_path]
set link_library [list your_library.db]
set target_library [list your_library.db]
set symbol_library [list your_library.sdb]
define_design_lib work -path work
@


1.3
log
@Now contains also the other file
@
text
@d1 5
a5 125
/* Defaults setup menu */
designer = "NISung"
company = "TSMC"
search_path = { ~ }
hdlin_translate_off_skip_text = TRUE
link_library= { }
target_library= { your_library.db }
symbol_library= { }
default_schematic_options = "-size infinite"

/* Site Specific Variables */
synthetic_library = {}
command_log_file = "./command.log"
view_command_log_file = "./view_command.log"
plot_command = "lpr -Plw"
text_print_command = "lpr -Plw"

/* enable Text Viewer feature */
hdlin_source_to_gates_mode = "high"

/* Synopsys to Compass EDIF interface */
edifin_ground_name = "VSS"
edifin_ground_net_name = "VSS"
edifin_ground_net_property_name = "global"
edifin_ground_net_property_value = "VSS"
edifin_ground_pin_name = "VSS"
edifin_ground_port_name = "VSS"
edifin_netlist_only = "true"
edifin_power_name = "VDD"
edifin_power_net_name = "VDD"
edifin_power_net_property_name = "global"
edifin_power_net_property_value = "VDD"
edifin_power_pin_name = "VDD"
edifin_power_port_name = "VDD"
edifin_power_and_ground_representation = "net"
edifout_ground_name = "VSS"
edifout_ground_net_name = "VSS"
edifout_ground_net_property_name = "global"
edifout_ground_net_property_value = "VSS"
edifout_ground_pin_name = "VSS"
edifout_ground_port_name = "VSS"
edifout_netlist_only = "true"
edifout_no_array = "true"
edifout_power_name = "VDD"
edifout_power_net_name = "VDD"
edifout_power_net_property_name = "global"
edifout_power_net_property_value = "VDD"
edifout_power_pin_name = "VDD"
edifout_power_port_name = "VDD"
edifout_power_and_ground_representation = "net"
write_name_nets_same_as_ports = "true"
compile_fix_multiple_port_nets = "true"
verilogout_no_tri = "true"

define_name_rules asic_top_rules \
-allowed "a-zA-Z0-9_()[]" \
-max_length 16 \
-reserved_words {"always", "and", "assign", "begin", "buf", "bufif0", \
 "bufif1", "case", "casex", "casez", "cmos", "deassign", "default", \
 "defparam", "disable", "edge", "else", "end", "endcase", "endfunction", \
 "endmodule", "endprimitive", "endspecify", "endtable", "endtask", \
 "event", "for", "force", "forever", "fork", "function", "highz0", \
 "highz1", "if", "initial", "inout", "input", "integer", "join", "large", \
 "macromodule", "medium", "module", "nand", "negedge", "nmos", "nor", \
 "not", "notif0", "notif1", "or", "output", "pmos", "posedge", "primitive", \
 "pull0", "pull1", "pulldown", "pullup", "rcmos", "reg", "release", "repeat", \
 "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "scalered", "small", \
 "specify", "specparam", "strong0", "strong1", "supply0", "supply1", \
 "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", \
 "tri1", "triand", "trior", "vectored", "wait", "wand", "weak0", "weak1", \
 "while", "wire", "wor", "xnor", "xor", \
 "abs", "access", "after", "alias", "all", "and", "architecture", "array", \
 "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", \
 "component", "configuration", "constant", "disconnect", "downto", "else", \
 "elsif", "end", "entity", "exit", "file", "for", "function", "generate", \
 "generic", "guarded", "if", "in", "inout", "is", "label", "library", \
 "linkage", "loop", "map", "mod", "nand", "new", "next", "nor", "not", \
 "null", "of", "on", "open", "or", "others", "out", "package", "port", \
 "procedure", "process", "range", "record", "register", "rem", "report", \
 "return", "select", "severity", "signal", "subtype", "then", "to", \
 "transport", "type", "units", "until", "use", "variable", "wait", "when", \
 "while", "with", "xor"} \
 -case_insensitive \
 -first_restricted "_" \
 -last_restricted "_" \
 -map {{"\*cell\*","U"},{"*-return","RET"}};

define_name_rules asic_core_rules \
-allowed "a-zA-Z0-9_()[]" \
-max_length 255 \
-reserved_words {"always", "and", "assign", "begin", "buf", "bufif0", \
 "bufif1", "case", "casex", "casez", "cmos", "deassign", "default", \
 "defparam", "disable", "edge", "else", "end", "endcase", "endfunction", \
 "endmodule", "endprimitive", "endspecify", "endtable", "endtask", \
 "event", "for", "force", "forever", "fork", "function", "highz0", \
 "highz1", "if", "initial", "inout", "input", "integer", "join", "large", \
 "macromodule", "medium", "module", "nand", "negedge", "nmos", "nor", \
 "not", "notif0", "notif1", "or", "output", "pmos", "posedge", "primitive", \
 "pull0", "pull1", "pulldown", "pullup", "rcmos", "reg", "release", "repeat", \
 "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "scalered", "small", \
 "specify", "specparam", "strong0", "strong1", "supply0", "supply1", \
 "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", \
 "tri1", "triand", "trior", "vectored", "wait", "wand", "weak0", "weak1", \
 "while", "wire", "wor", "xnor", "xor", \
 \
 "abs", "access", "after", "alias", "all", "and", "architecture", "array", \
 "assert", "attribute", "begin", "block", "body", "buffer", "bus", "case", \
 "component", "configuration", "constant", "disconnect", "downto", "else", \
 "elsif", "end", "entity", "exit", "file", "for", "function", "generate", \
 "generic", "guarded", "if", "in", "inout", "is", "label", "library", \
 "linkage", "loop", "map", "mod", "nand", "new", "next", "nor", "not", \
 "null", "of", "on", "open", "or", "others", "out", "package", "port", \
 "procedure", "process", "range", "record", "register", "rem", "report", \
 "return", "select", "severity", "signal", "subtype", "then", "to", \
 "transport", "type", "units", "until", "use", "variable", "wait", "when", \
 "while", "with", "xor"} \
 -case_insensitive \
 -last_restricted "_" \
 -first_restricted "_" \
 -map {{"\*cell\*","U"},{"*-return","RET"}};

view_script_submenu_items = view_script_submenu_items + \
{"Apply Name Rules", "change_names -rules asic_core_rules -verbose \
-hierarchy; change_names -rules asic_top_rules -verbose" }  

@


1.2
log
@Version with undisclosed library names
@
text
@d1 1
a1 1
/* setup the Setup...Defaults menu */
d4 1
a4 1
search_path = { /usr/design/techlibs/tsmc/digital/Front_End/timing_power/tcbn90lphpcg_150a }
d7 1
a7 1
target_library= { tcbn90lphpcgtc.db }
d54 72
a125 1
include TSMC_naming_rule.script
@


1.1
log
@Initial version
B
C
C
Initial versioNCVS: ----------------------------------------------------------------------
@
text
@d4 1
a4 1
search_path = { } 
d7 1
a7 1
target_library= { }
@