head	1.2;
access;
symbols;
locks; strict;
comment	@# @;


1.2
date	2007.03.27.00.33.08;	author fafa1971;	state Exp;
branches;
next	1.1;
commitid	487e4608662a4567;

1.1
date	2007.01.04.02.22.22;	author fafa1971;	state Exp;
branches;
next	;
commitid	34a459c64d94567;


desc
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1.2
log
@Removed list of formerly dirty signals, to improve waveforms readability.
@
text
@*-21,125721 7674010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@@28
testbench.sys_reset
testbench.sys_clock
testbench.s1_top_0.gclk
(0)testbench.s1_top_0.spc_pcx_req_pq[4:0]
(1)testbench.s1_top_0.spc_pcx_req_pq[4:0]
(2)testbench.s1_top_0.spc_pcx_req_pq[4:0]
(3)testbench.s1_top_0.spc_pcx_req_pq[4:0]
(4)testbench.s1_top_0.spc_pcx_req_pq[4:0]
testbench.s1_top_0.spc_pcx_atom_pq
@@22
testbench.s1_top_0.spc_pcx_data_pa[123:0]
testbench.s1_top_0.pcx_spc_grant_px[4:0]
@@28
testbench.s1_top_0.cpx_spc_data_rdy_cx2
@@22
testbench.s1_top_0.cpx_spc_data_cx2[144:0]
@@28
testbench.wb_cycle
testbench.wb_strobe
@@22
testbench.wb_sel[7:0]
@@28
testbench.wb_we
@@22
testbench.wb_addr[63:0]
testbench.wb_dataout[63:0]
@@28
testbench.wb_ack
@@22
testbench.wb_datain[63:0]
@


1.1
log
@First version.
@
text
@d1 1
a1 1
*-15.938658 7196010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
a32 86
@@28
testbench.s1_top_0.sparc_0.exu.ecl.lsu_exu_flush_pipe_w
testbench.s1_top_0.sparc_0.exu.ecl.mdqctl.div_kill
testbench.s1_top_0.sparc_0.exu.ecl.mdqctl.flush_w1
testbench.s1_top_0.sparc_0.exu.ecl.mdqctl.mul_kill
testbench.s1_top_0.sparc_0.exu.ecl.writeback.ecl_exu_kill_m
testbench.s1_top_0.sparc_0.exu.ecl.writeback.flush_w1
testbench.s1_top_0.sparc_0.exu.ecl.writeback.kill_ld_g2
testbench.s1_top_0.sparc_0.exu.lsu_exu_flush_pipe_w
testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_dff.din[0]
testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_dff.q[0]
testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_dff.so[0]
testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_m
testbench.s1_top_0.sparc_0.ffu.ctl.dff_flush_w2.din[0]
testbench.s1_top_0.sparc_0.ffu.ctl.dff_flush_w2.q[0]
testbench.s1_top_0.sparc_0.ffu.ctl.dff_flush_w2.so[0]
testbench.s1_top_0.sparc_0.ffu.ctl.dff_killed_w.din[0]
testbench.s1_top_0.sparc_0.ffu.ctl.flush_w
testbench.s1_top_0.sparc_0.ffu.ctl.flush_w2
testbench.s1_top_0.sparc_0.ffu.ctl.ieee_trap
testbench.s1_top_0.sparc_0.ffu.ctl.kill_fp
testbench.s1_top_0.sparc_0.ffu.ctl.kill_m
testbench.s1_top_0.sparc_0.ffu.ctl.lsu_ffu_blk_asi_e
testbench.s1_top_0.sparc_0.ffu.ctl.lsu_ffu_flush_pipe_w
testbench.s1_top_0.sparc_0.ffu.ctl.visctl.flush_w2
testbench.s1_top_0.sparc_0.ffu.lsu_ffu_blk_asi_e
testbench.s1_top_0.sparc_0.ffu.lsu_ffu_flush_pipe_w
testbench.s1_top_0.sparc_0.ifu.dcl.all_flush_w
testbench.s1_top_0.sparc_0.ifu.dcl.all_flush_w2
testbench.s1_top_0.sparc_0.ifu.dcl.flshw2_ff.so[0]
testbench.s1_top_0.sparc_0.ifu.dcl.tlu_ifu_flush_pipe_w
testbench.s1_top_0.sparc_0.ifu.dec.dtu_fcl_flush_sonly_e
testbench.s1_top_0.sparc_0.ifu.dtu_fcl_flush_sonly_e
testbench.s1_top_0.sparc_0.ifu.fcl.canthr_sd
testbench.s1_top_0.sparc_0.ifu.fcl.canthr_sm
testbench.s1_top_0.sparc_0.ifu.fcl.canthr_sw
testbench.s1_top_0.sparc_0.ifu.fcl.dtu_fcl_flush_sonly_e
testbench.s1_top_0.sparc_0.ifu.fcl.ely_kill_thread_m
testbench.s1_top_0.sparc_0.ifu.fcl.ely_kill_thread_s2
testbench.s1_top_0.sparc_0.ifu.fcl.fcl_fdp_noswpc_sel_old_l_bf
testbench.s1_top_0.sparc_0.ifu.fcl.fcl_fdp_noswpc_sel_tnpc_l_bf
testbench.s1_top_0.sparc_0.ifu.fcl.fcl_fdp_pcoor_f
testbench.s1_top_0.sparc_0.ifu.fcl.flshm_ff.din[0]
testbench.s1_top_0.sparc_0.ifu.fcl.flshm_ff.q[0]
testbench.s1_top_0.sparc_0.ifu.fcl.flshm_ff.so[0]
testbench.s1_top_0.sparc_0.ifu.fcl.flush_pipe_w
testbench.s1_top_0.sparc_0.ifu.fcl.flush_pipe_w2
testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_all_m
testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_m
testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_qual_e
testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_qual_m
testbench.s1_top_0.sparc_0.ifu.fcl.fp_ff.din[0]
testbench.s1_top_0.sparc_0.ifu.fcl.fp_ff.q[0]
testbench.s1_top_0.sparc_0.ifu.fcl.fp_ff.so[0]
testbench.s1_top_0.sparc_0.ifu.fcl.fdp_fcl_va2_bf
testbench.s1_top_0.sparc_0.ifu.fcl.itlb_access_gnt
testbench.s1_top_0.sparc_0.ifu.fcl.itlbrstf_ff.din[0]
testbench.s1_top_0.sparc_0.ifu.fcl.kill_thread_d
testbench.s1_top_0.sparc_0.ifu.fcl.kill_thread_m
testbench.s1_top_0.sparc_0.ifu.fcl.kill_thread_s2
testbench.s1_top_0.sparc_0.ifu.fcl.kill_curr_m
testbench.s1_top_0.sparc_0.ifu.fcl.ntpc_thisthr
testbench.s1_top_0.sparc_0.ifu.fcl.rst_itlb_stv_l
testbench.s1_top_0.sparc_0.ifu.fcl.starv_ctr.rst_ctr_l
testbench.s1_top_0.sparc_0.ifu.fcl.tlu_ifu_trapnpc_vld_w1
testbench.s1_top_0.sparc_0.ifu.fcl.tlu_ifu_trappc_vld_w1
testbench.s1_top_0.sparc_0.ifu.fcl.tlu_ifu_flush_pipe_w
testbench.s1_top_0.sparc_0.ifu.fcl.va2_f
testbench.s1_top_0.sparc_0.ifu.fcl.va2_ff.din[0]
testbench.s1_top_0.sparc_0.ifu.fcl.va2_ff.q[0]
testbench.s1_top_0.sparc_0.ifu.fcl.va2_ff.so[0]
testbench.s1_top_0.sparc_0.ifu.fcl_fdp_noswpc_sel_old_l_bf
testbench.s1_top_0.sparc_0.ifu.fcl_fdp_noswpc_sel_tnpc_l_bf
testbench.s1_top_0.sparc_0.ifu.fcl_fdp_pcoor_f
testbench.s1_top_0.sparc_0.ifu.fdp.fcl_fdp_noswpc_sel_tnpc_l_bf
testbench.s1_top_0.sparc_0.ifu.fdp.fcl_fdp_pcoor_f
testbench.s1_top_0.sparc_0.ifu.fdp.t0_pcbf_mux.sel0_l
testbench.s1_top_0.sparc_0.ifu.fdp.t0_pcbf_mux.sel2_l
testbench.s1_top_0.sparc_0.ifu.fdp.t0tnpc_mux.sel3_l
testbench.s1_top_0.sparc_0.ifu.fdp.t0tnpc_mux.sel2_l
testbench.s1_top_0.sparc_0.ifu.ifqctl.cans_ff.din[0]
testbench.s1_top_0.sparc_0.ifu.ifqctl.canthr_d1
testbench.s1_top_0.sparc_0.ifu.ifqctl.canthr_s1
testbench.s1_top_0.sparc_0.ifu.ifqctl.mil0.cancel_mil
testbench.s1_top_0.sparc_0.ifu.ifqctl.mil0.cancel_next
testbench.s1_top_0.sparc_0.ifu.ifqctl.mil0.fsm_ifc_mil_cancel
@