head	1.11;
access;
symbols;
locks; strict;
comment	@:: @;


1.11
date	2008.03.10.13.22.51;	author fafa1971;	state Exp;
branches;
next	1.10;
commitid	491647d5360d4567;

1.10
date	2008.03.10.10.43.35;	author fafa1971;	state Exp;
branches;
next	1.9;
commitid	794b47d510ba4567;

1.9
date	2008.03.03.15.00.32;	author fafa1971;	state Exp;
branches;
next	1.8;
commitid	472347cc12784567;

1.8
date	2008.02.21.15.03.46;	author fafa1971;	state Exp;
branches;
next	1.7;
commitid	ff147bd92b54567;

1.7
date	2008.02.21.11.40.40;	author fafa1971;	state Exp;
branches;
next	1.6;
commitid	2af147bd63224567;

1.6
date	2008.02.18.15.47.29;	author fafa1971;	state Exp;
branches;
next	1.5;
commitid	6a5447b9a8824567;

1.5
date	2008.02.18.15.45.21;	author fafa1971;	state Exp;
branches;
next	1.4;
commitid	692747b9a7ff4567;

1.4
date	2007.11.10.18.35.38;	author fafa1971;	state Exp;
branches;
next	1.3;
commitid	73e64735f9e04567;

1.3
date	2007.11.10.13.58.09;	author fafa1971;	state Exp;
branches;
next	1.2;
commitid	655a4735b8db4567;

1.2
date	2007.10.24.21.50.55;	author fafa1971;	state Exp;
branches;
next	1.1;
commitid	1ba7471fbe324567;

1.1
date	2007.01.04.02.22.22;	author fafa1971;	state Exp;
branches;
next	;
commitid	34a459c64d94567;


desc
@@


1.11
log
@GREAT synthesis script!!! Performs all bottom-up synthesis without errors.
@
text
@
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!

# Variables setting

set sub_modules {sparc_ifu lsu sparc_exu sparc_ffu sparc_mul_top spu tlu s1_top}
set sub_clocks  {rclk clk sys_clock_i}
set sub_resets  {grst_l arst_l sys_reset_i}

foreach active_design $sub_modules {

  # Technology-independent elaboration and linking
  elaborate      $active_design
  current_design $active_design
  link
  uniquify -dont_skip_empty_designs

  # Set constraints and mapping on target library
  create_clock -period 5.0 -waveform [list 0 2.5] [get_ports $sub_clocks]
  set_input_delay  1.8 -clock [get_clocks $sub_clocks] -max [all_inputs]
  set_output_delay 1.2 -clock [get_clocks $sub_clocks] -max [all_outputs]
  set_dont_touch_network [concat $sub_clocks $sub_resets]
  set_drive    0         [concat $sub_clocks $sub_resets]
  set_max_area 0
  set_wire_load_mode enclosed
  set_fix_multiple_port_nets -buffer_constants -all
  compile

  # Export the mapped design
  remove_unconnected_ports [find -hierarchy cell {"*"}]
  set_dont_touch current_design
  write -format ddc -hierarchy -output $active_design.ddc
  write -format verilog -hierarchy -output $active_design.sv

  # Report area and timing
  report_area -hierarchy > report_${active_design}_area.rpt
  report_timing > report_${active_design}_timing.rpt
  report_constraint -all_violators > report_${active_design}_constraint.rpt

}

quit

@


1.10
log
@Again, used module names instead than instance names in bottom-up synthesis approach.
@
text
@d7 1
a7 1
set sub_modules {ifu lsu exu ffu mul spu tlu s1_top}
d23 2
a24 2
  set_dont_touch_network [list $sub_clocks $sub_resets]
  set_drive    0         [list $sub_clocks $sub_resets]
d28 1
a28 1
  compile -map_effort low
@


1.9
log
@Decreased clock frequency from 250 to 200 MHz.
@
text
@d5 1
a5 1
# Technology-independent elaboration and linking
d7 35
a41 30
set active_design s1_top
elaborate $active_design
current_design $active_design
link
uniquify
check_design

# Constraints and mapping on target library

create_clock -period 5.0 -waveform [list 0 2.5] sys_clock_i
set_input_delay  2.0 -clock sys_clock_i -max [all_inputs]
set_output_delay 2.0 -clock sys_clock_i -max [all_outputs]
set_dont_touch_network [list sys_clock_i sys_reset_i]
set_drive 0 [list sys_clock_i sys_reset_i]
set_wire_load_mode enclosed
set_max_area 0
set_fix_multiple_port_nets -buffer_constants -all
compile

# Export the mapped design

remove_unconnected_ports [find -hierarchy cell {"*"}]
write -format ddc -hierarchy -output $active_design.ddc
write -format verilog -hierarchy -output $active_design.sv

# Report area and timing

report_area -hierarchy > report_area.rpt
report_timing > report_timing.rpt
report_constraint -all_violators > report_constraint.rpt
@


1.8
log
@DC synthesis script modified according to the fabolous manual (RTFM...).
@
text
@d16 3
a18 3
create_clock -period 4.0 -waveform [list 0 2.0] sys_clock_i
set_input_delay 2.0 -clock sys_clock_i -max [all_inputs]
set_output_delay 1.0 -clock sys_clock_i -max [all_outputs]
@


1.7
log
@Sorry, I made a mistake in the waveform of the clock!
@
text
@d5 5
a9 1
elaborate s1_top
d14 1
a14 11
# Constraints

create_clock -name "sys_clock_i" -period 4.0 -waveform {0 2.0} [get_ports "sys_clock_i"]
set_dont_touch_network [get_clocks "sys_clock_i"]
set_input_delay 2.50 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_input_delay 2.50 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_output_delay 2.50 -clock sys_clock_i -max -rise [all_outputs]
set_output_delay 2.50 -clock sys_clock_i -max -fall [all_outputs]
set_wire_load_mode "enclosed" 

# Compile
d16 8
d26 1
a26 1
# Export
d28 3
a30 2
write -format ddc -hierarchy -output "s1_top.ddc"
write -format verilog -hierarchy -output "s1_top.v"
d32 1
a32 1
# Report
d34 3
a36 3
report_area -hierarchy > report_area.txt
report_timing > report_timing.txt
report_constraint -all_violators > report_constraint.txt
@


1.6
log
@Hyerarchical report_area.
@
text
@d1 1
a8 1
flatten s1_top
d12 1
a12 1
create_clock -name "sys_clock_i" -period 4.0 -waveform {0 1.0} [get_ports "sys_clock_i"]
@


1.5
log
@Relaxed timing and added flatten command.
@
text
@d31 1
a31 1
report_area > report_area.txt
@


1.4
log
@Changed again from DB export to DDC export
@
text
@d8 1
d12 1
a12 1
create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]
d14 4
a17 4
set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]
set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]
set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]
@


1.3
log
@New version of scripts for DC and to compile boot code
@
text
@d25 1
a25 1
write -format db -hierarchy -output "s1_top.db"
@


1.2
log
@Modified to use XG syntax
@
text
@d1 2
a2 2

/* If you modify this file remember to run update_filelist so that filelist.dc gets updated!!! */
d7 15
a21 1
/* check_design */
d23 1
a23 3
create_clock -period 2.0 -name sys_clock_i find(port, "sys_clock_i")
set_input_delay  -max -clock sys_clock_i 1 all_inputs () find (port, "sys_clock_i")
set_output_delay 1 -max -clock sys_clock_i all_outputs()
d25 2
a26 1
compile -map_effort high
d28 1
a28 2
write -output s1_top.db  -format ddc  -hierarchy
write -output s1_top.v  -format verilog  -hierarchy
@


1.1
log
@First version.
@
text
@d10 1
a10 1
set_input_delay  1 -max -clock sys_clock_i all_inputs() - find(port, "sys_clock_i")
d15 2
a16 2
write -format db -hierarchy -output s1_top.db
write -format verilog -hierarchy -output s1_top.v
@