head	1.3;
access;
symbols;
locks; strict;
comment	@# @;


1.3
date	2007.01.14.03.20.37;	author jlechner;	state Exp;
branches;
next	1.2;
commitid	335d45a9a1834567;

1.2
date	2007.01.12.23.15.22;	author jlechner;	state Exp;
branches;
next	1.1;
commitid	a7045a816864567;

1.1
date	2006.12.31.18.55.35;	author jlechner;	state Exp;
branches;
next	;
commitid	47a4459807a44567;


desc
@@


1.3
log
@Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation
@
text
@-------------------------------------------------------------------------------
-- File: ex_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-12-31
-- Last updated: 2006-12-31

-- Description:
-- Testbench for RLU unit
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.rise_pack.all;
use work.RISE_PACK_SPECIFIC.all;

entity tb_rlu_unit_vhd is
end tb_rlu_unit_vhd;

architecture behavior of tb_rlu_unit_vhd is

  -- component Declaration for the Unit Under Test (UUT)
  component rlu is

                  port (
                    clk   : in std_logic;
                    reset : in std_logic;

                    lock_register : out LOCK_REGISTER_T;

                    set_lock0      : in std_logic;
                    set_lock_addr0 : in REGISTER_ADDR_T;

                    set_lock1      : in std_logic;
                    set_lock_addr1 : in REGISTER_ADDR_T;

                    clear_lock0      : in std_logic;
                    clear_lock_addr0 : in REGISTER_ADDR_T;

                    clear_lock1      : in std_logic;
                    clear_lock_addr1 : in REGISTER_ADDR_T);

  end component;

  constant clk_period : time := 10 ns;

  --inputs
  signal clk   : std_logic := '0';
  signal reset : std_logic := '0';

  signal clear_lock0_sig      : std_logic := '0';
  signal clear_lock_addr0_sig : REGISTER_ADDR_T;

  signal clear_lock1_sig      : std_logic := '0';
  signal clear_lock_addr1_sig : REGISTER_ADDR_T;

  signal set_lock0_sig      : std_logic := '0';
  signal set_lock_addr0_sig : REGISTER_ADDR_T;

  signal set_lock1_sig      : std_logic := '0';
  signal set_lock_addr1_sig : REGISTER_ADDR_T;

  --Outputs
  signal lock_register : LOCK_REGISTER_T;

begin

  -- instantiate the Unit Under Test (UUT)
  uut : rlu port map(
    clk                 => clk,
    reset               => reset,

    lock_register       => lock_register,

    set_lock0           => set_lock0_sig,
    set_lock_addr0      => set_lock_addr0_sig,

    set_lock1           => set_lock1_sig,
    set_lock_addr1      => set_lock_addr1_sig,

    clear_lock0         => clear_lock0_sig,
    clear_lock_addr0    => clear_lock_addr0_sig,

    clear_lock1         => clear_lock1_sig,
    clear_lock_addr1    => clear_lock_addr1_sig);


  cg : process
  begin
    clk <= '1';
    wait for clk_period/2;
    clk <= '0';
    wait for clk_period/2;
  end process;

  tb : process
  begin
    reset <= '0';
    wait for 10 * clk_period;
    reset <= '1';


    set_lock_addr0_sig     <= CONV_STD_LOGIC_VECTOR(8, REGISTER_ADDR_WIDTH);
    set_lock0_sig <= '1';
    wait for clk_period;
    set_lock_addr0_sig     <= CONV_STD_LOGIC_VECTOR(9, REGISTER_ADDR_WIDTH);
    set_lock0_sig <= '1';
    set_lock_addr1_sig     <= SR_REGISTER_ADDR;
    set_lock1_sig <= '1';
    clear_lock_addr0_sig   <= CONV_STD_LOGIC_VECTOR(8, REGISTER_ADDR_WIDTH);
    clear_lock0_sig <= '1';
    
    wait;                               -- will wait forever
  end process;

end;
@


1.2
log
@Modified input signals for register locking (testbench modifications):
Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle
there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).
@
text
@d17 1
@


1.1
log
@Implementation of execute stage and register lock unit. Some changes im RISE package.
@
text
@d25 18
a42 10
  
  port (
    clk                 : in std_logic;
    reset               : in std_logic;

    lock_register       : out LOCK_REGISTER_T;

    clear_reg_lock      : in std_logic;
    set_reg_lock        : in std_logic;
    reg_addr            : in REGISTER_ADDR_T);
d45 1
a45 1
    
d49 15
a63 6
  signal clk            : std_logic := '0';
  signal reset          : std_logic := '0';
  signal clear_reg_lock : std_logic := '0';
  signal set_reg_lock   : std_logic := '0';
  signal reg_addr       : REGISTER_ADDR_T;
  
d66 1
a66 1
  
d71 4
a74 3
    clk             => clk,
    reset           => reset,
    lock_register   => lock_register, 
d76 11
a86 3
    clear_reg_lock  => clear_reg_lock,
    set_reg_lock    => set_reg_lock,
    reg_addr        => reg_addr);
a88 1
  
d104 2
a105 9
    reg_addr <= CONV_STD_LOGIC_VECTOR(8, REGISTER_ADDR_WIDTH);
    set_reg_lock <= '1';
    wait for clk_period;
    reg_addr <= CONV_STD_LOGIC_VECTOR(5, REGISTER_ADDR_WIDTH);
    set_reg_lock <= '1';
    wait for clk_period;
    set_reg_lock <= '0';
    reg_addr <= CONV_STD_LOGIC_VECTOR(8, REGISTER_ADDR_WIDTH);
    clear_reg_lock <= '1';
d107 6
a112 1
    clear_reg_lock <= '0';
@