head	1.3;
access;
symbols;
locks; strict;
comment	@# @;


1.3
date	2007.01.14.03.20.37;	author jlechner;	state Exp;
branches;
next	1.2;
commitid	335d45a9a1834567;

1.2
date	2007.01.13.20.00.38;	author cwalter;	state Exp;
branches;
next	1.1;
commitid	660645a93a634567;

1.1
date	2007.01.12.22.52.15;	author cwalter;	state Exp;
branches;
next	;
commitid	7f5945a8111d4567;


desc
@@


1.3
log
@Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation
@
text
@-- File: ex_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29

-- Description:
-- Execute stage
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.rise_pack.all;
use work.RISE_PACK_SPECIFIC.all;

entity tb_rise_vhd is
end tb_rise_vhd;

architecture behavior of tb_rise_vhd is

  component rise
    port(
      clk   : in  std_logic;
      reset : in  std_logic;
      rx    : in  std_logic;
      tx    : out std_logic
      );
  end component;

  --Inputs
  signal clk   : std_logic := '0';
  signal reset : std_logic := '0';
  signal rx    : std_logic := '0';

  --Outputs
  signal tx : std_logic;

begin

  -- Instantiate the Unit Under Test (UUT)
  uut : rise port map(
    clk   => clk,
    reset => reset,
    rx    => rx,
    tx    => tx
    );

  clk_gen : process
  begin
    clk <= '1';
    wait for 10 ns;
    clk <= '0';
    wait for 10 ns;
  end process;

  tb : process
  begin

    wait for 5 ns;

    -- Place stimulus here
    reset <= '1';

    -- Let the simulation run for 200 ns;
    wait for 200 ns;

    wait;
  end process;

end;
@


1.2
log
@ - Changed reset delay.
@
text
@d15 1
@


1.1
log
@ - Testbench for RISE.
@
text
@d59 1
a59 2
    -- Wait 100 ns for global reset to finish
    wait for 95 ns;
@