head	1.7;
access;
symbols;
locks; strict;
comment	@# @;


1.7
date	2007.01.14.17.44.31;	author jlechner;	state Exp;
branches;
next	1.6;
commitid	5a1c45aa6bfa4567;

1.6
date	2007.01.14.14.27.18;	author cwalter;	state Exp;
branches;
next	1.5;
commitid	33d145aa3dc34567;

1.5
date	2007.01.14.03.20.37;	author jlechner;	state Exp;
branches;
next	1.4;
commitid	335d45a9a1834567;

1.4
date	2007.01.12.23.13.41;	author jlechner;	state Exp;
branches;
next	1.3;
commitid	9c945a816214567;

1.3
date	2007.01.06.00.01.19;	author cwalter;	state Exp;
branches;
next	1.2;
commitid	6412459ee6cc4567;

1.2
date	2006.12.31.18.55.35;	author jlechner;	state Exp;
branches;
next	1.1;
commitid	47a4459807a44567;

1.1
date	2006.12.06.22.41.04;	author jlechner;	state Exp;
branches;
next	;
commitid	6319457746fd4567;


desc
@@


1.7
log
@Added input signal for clearing all register locks.
@
text
@-- File: rlu.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29

-- Description:
-- Register Lock Unit (Provides flags for locking access to registers).
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use WORK.RISE_PACK.all;
use WORK.RISE_PACK_SPECIFIC.all;

entity rlu is
  
  port (
    clk   : in std_logic;
    reset : in std_logic;
    clear_locks : in std_logic;
    
    lock_register       : out LOCK_REGISTER_T;

    set_lock0           : in std_logic;
    set_lock_addr0      : in REGISTER_ADDR_T;

    set_lock1           : in std_logic;
    set_lock_addr1      : in REGISTER_ADDR_T;
    
    clear_lock0         : in std_logic;
    clear_lock_addr0    : in REGISTER_ADDR_T;
    
    clear_lock1         : in std_logic;
    clear_lock_addr1    : in REGISTER_ADDR_T);

end rlu;


architecture rlu_rtl of rlu is

  signal lock_register_int  : LOCK_REGISTER_T;
  signal lock_register_next : LOCK_REGISTER_T;
  
begin  -- rlu_rtl

  lock_register <= lock_register_int;

  sync : process (clk, reset)
  begin  -- process
    if reset = '0' then                 -- asynchronous reset (active low)
      lock_register_int <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if clear_locks = '1' then
        lock_register_int <= (others => '0');
      else
        lock_register_int <= lock_register_next;
      end if;
    end if;
  end process;

  async : process (lock_register_int,
                   clear_lock0, set_lock0,
                   clear_lock1, set_lock1, 
                   clear_lock_addr0, set_lock_addr0,
                   clear_lock_addr1, set_lock_addr1)
  begin  -- process async
    lock_register_next <= lock_register_int;

    -- first unlock all possible registers and then lock them. because
    -- the last assignment counts this also works correct if reg_addr0
    -- and reg_addr1 are the same and one unlocks and one locks the
    -- register (correct behaviour is that the register is locked).

    -- clear register0 lock
    if clear_lock0 = '1' then
      lock_register_next(to_integer(unsigned(clear_lock_addr0))) <= '0';
    end if;
    -- clear register1 lock
    if clear_lock1 = '1' then
      lock_register_next(to_integer(unsigned(clear_lock_addr1))) <= '0';
    end if;
    -- set register0 lock
    if set_lock0 = '1' then
      lock_register_next(to_integer(unsigned(set_lock_addr0))) <= '1';
    end if;
    -- set register1 lock
    if set_lock1 = '1' then
      lock_register_next(to_integer(unsigned(set_lock_addr1))) <= '1';
    end if;
    
  end process async;

end rlu_rtl;
@


1.6
log
@ - Fixed case.
@
text
@d21 2
a22 1

d54 5
a58 1
      lock_register_int <= lock_register_next;
@


1.5
log
@Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation
@
text
@d12 1
a12 1
use IEEE.numeric_std.all;
d14 1
a14 1
use work.RISE_PACK_SPECIFIC.all;
@


1.4
log
@Modified input signals for register locking:
Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle
there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).
@
text
@d14 1
a14 1

@


1.3
log
@ - Renamed clear/set_reg_lock to clear/set_reg_lock0.
 - Added second register locking port reg_lock1.
@
text
@d22 1
a22 1
    lock_register : out LOCK_REGISTER_T;
d24 11
a34 7
    clear_reg_lock0 : in std_logic;
    set_reg_lock0   : in std_logic;
    reg_addr0       : in REGISTER_ADDR_T;

    clear_reg_lock1 : in std_logic;
    set_reg_lock1   : in std_logic;
    reg_addr1       : in REGISTER_ADDR_T);
d58 4
a61 2
                   clear_reg_lock0, set_reg_lock0, reg_addr0,
                   clear_reg_lock1, set_reg_lock1, reg_addr1)
d69 4
a72 2
    if clear_reg_lock0 = '1' and set_reg_lock0 = '0' then
      lock_register_next(to_integer(unsigned(reg_addr0))) <= '0';
d74 3
a76 2
    if clear_reg_lock1 = '1' and set_reg_lock1 = '0' then
      lock_register_next(to_integer(unsigned(reg_addr1))) <= '0';
d78 3
a80 2
    if set_reg_lock0 = '1' and clear_reg_lock0 = '0' then
      lock_register_next(to_integer(unsigned(reg_addr0))) <= '1';
d82 3
a84 2
    if set_reg_lock1 = '1' and clear_reg_lock1 = '0' then
      lock_register_next(to_integer(unsigned(reg_addr1))) <= '1';
@


1.2
log
@Implementation of execute stage and register lock unit. Some changes im RISE package.
@
text
@d19 2
a20 2
    clk                 : in std_logic;
    reset               : in std_logic;
d22 1
a22 1
    lock_register       : out LOCK_REGISTER_T;
d24 7
a30 3
    clear_reg_lock      : in std_logic;
    set_reg_lock        : in std_logic;
    reg_addr            : in REGISTER_ADDR_T);
d37 2
a38 2
  signal lock_register_int      : LOCK_REGISTER_T;
  signal lock_register_next     : LOCK_REGISTER_T;
d43 2
a44 2
  
  sync: process (clk, reset)
d53 3
a55 1
  async: process (lock_register_int, clear_reg_lock, set_reg_lock, reg_addr)
d59 12
a70 2
    if clear_reg_lock = '1' and set_reg_lock = '0' then
      lock_register_next(to_integer(unsigned(reg_addr))) <= '0';     
d72 2
a73 2
    if set_reg_lock = '1' and clear_reg_lock = '0' then
      lock_register_next(to_integer(unsigned(reg_addr))) <= '1';     
d75 1
a75 1
      
@


1.1
log
@Initial commit of project
@
text
@d12 1
a12 2
use IEEE.STD_LOGIC_ARITH.all;

d33 3
d38 1
d40 21
@