head	1.12;
access;
symbols;
locks; strict;
comment	@# @;


1.12
date	2007.01.24.15.36.24;	author trinklhar;	state Exp;
branches;
next	1.11;
commitid	379245b77cf44567;

1.11
date	2007.01.24.14.26.15;	author trinklhar;	state Exp;
branches;
next	1.10;
commitid	1e545b76c864567;

1.10
date	2007.01.23.19.24.22;	author trinklhar;	state Exp;
branches;
next	1.9;
commitid	43c145b660e54567;

1.9
date	2007.01.14.03.18.40;	author jlechner;	state Exp;
branches;
next	1.8;
commitid	323345a9a10f4567;

1.8
date	2007.01.13.20.00.10;	author cwalter;	state Exp;
branches;
next	1.7;
commitid	659e45a93a484567;

1.7
date	2007.01.13.15.00.26;	author cwalter;	state Exp;
branches;
next	1.6;
commitid	15d045a8f4074567;

1.6
date	2007.01.12.23.09.28;	author jlechner;	state Exp;
branches;
next	1.5;
commitid	86145a815234567;

1.5
date	2007.01.12.20.45.45;	author cwalter;	state Exp;
branches;
next	1.4;
commitid	3f7a45a7f3774567;

1.4
date	2007.01.03.02.12.30;	author cwalter;	state Exp;
branches;
next	1.3;
commitid	3fee459b110d4567;

1.3
date	2006.12.31.18.55.35;	author jlechner;	state Exp;
branches;
next	1.2;
commitid	47a4459807a44567;

1.2
date	2006.12.13.02.05.05;	author cwalter;	state Exp;
branches;
next	1.1;
commitid	17f7457f5fd04567;

1.1
date	2006.12.06.22.41.04;	author jlechner;	state Exp;
branches;
next	;
commitid	6319457746fd4567;


desc
@@


1.12
log
@Added constant for cpu frequency (needed for UART)
@
text
@-------------------------------------------------------------------------------
-- File: rise_pack.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29

-- Description:
-- Package for RISE project.
-------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use work.RISE_PACK_SPECIFIC.all;

package RISE_PACK is

  constant CLK_FREQ  : integer := 50000000;
  constant ARCHITECTURE_WIDTH : integer := 16;
  constant REGISTER_COUNT : integer := 16;
  
  constant PC_WIDTH : integer := ARCHITECTURE_WIDTH;
  constant IR_WIDTH : integer := ARCHITECTURE_WIDTH;
  constant SR_WIDTH : integer := ARCHITECTURE_WIDTH;
  constant MEM_DATA_WIDTH : integer := ARCHITECTURE_WIDTH;
  constant MEM_ADDR_WIDTH : integer := ARCHITECTURE_WIDTH;
  
  constant REGISTER_WIDTH : integer := ARCHITECTURE_WIDTH;
  constant REGISTER_ADDR_WIDTH : integer := 4;
  constant IMMEDIATE_WIDTH : integer := ARCHITECTURE_WIDTH;
  constant LOCK_WIDTH : integer := REGISTER_COUNT;

  constant ALUOP1_WIDTH : integer := 3;
  constant ALUOP2_WIDTH : integer := 3;
  
  subtype PC_REGISTER_T is std_logic_vector(PC_WIDTH-1 downto 0);
  subtype IR_REGISTER_T is std_logic_vector(IR_WIDTH-1 downto 0);
  subtype SR_REGISTER_T is std_logic_vector(SR_WIDTH-1 downto 0);
  subtype REGISTER_T is std_logic_vector(REGISTER_WIDTH-1 downto 0);
  subtype REGISTER_ADDR_T is std_logic_vector(REGISTER_ADDR_WIDTH-1 downto 0);
  subtype MEM_DATA_T is std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
  subtype MEM_ADDR_T is std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);

  subtype LOCK_REGISTER_T is std_logic_vector(LOCK_WIDTH-1 downto 0);
  
  subtype IMMEDIATE_T is std_logic_vector(IMMEDIATE_WIDTH-1 downto 0);

  subtype ALUOP1_T is std_logic_vector(ALUOP1_WIDTH-1 downto 0);
  subtype ALUOP2_T is std_logic_vector(ALUOP2_WIDTH-1 downto 0);

  --
  constant SR_REGISTER_ADDR : REGISTER_ADDR_T := "1111";
  constant PC_REGISTER_ADDR : REGISTER_ADDR_T := "1110";
  constant LR_REGISTER_ADDR : REGISTER_ADDR_T := "1101";
  
  constant SR_REGISTER_DI : INTEGER := 15;
  constant SR_REGISTER_IP_MASK : INTEGER := 12;
  constant SR_REGISTER_OVERFLOW : INTEGER := 3;
  constant SR_REGISTER_NEGATIVE : INTEGER := 2;
  constant SR_REGISTER_CARRY : INTEGER := 1;
  constant SR_REGISTER_ZERO : INTEGER := 0;
  constant RESET_PC_VALUE : PC_REGISTER_T := ( others => '0' );
  constant RESET_SR_VALUE : PC_REGISTER_T := ( others => '0' );

  constant PC_ADDR : REGISTER_ADDR_T := CONV_STD_LOGIC_VECTOR(14, REGISTER_ADDR_WIDTH);
  
  constant PC_RESET_VECTOR : MEM_ADDR_T := x"FFFE";
  
  
  -- STATUS REGISTER BITS --
  constant SR_ZERO_BIT          : integer := 0;
  constant SR_CARRY_BIT         : integer := 1;
  constant SR_NEGATIVE_BIT      : integer := 2;
  constant SR_OVERFLOW_BIT      : integer := 3;
  
  type IF_ID_REGISTER_T is record
                             pc : PC_REGISTER_T;
                             ir : IR_REGISTER_T;
                           end record;

  type ID_EX_REGISTER_T is record
                             sr         : SR_REGISTER_T;
                             pc         : PC_REGISTER_T;
                             opcode     : OPCODE_T;
                             cond       : COND_T;
                             rX_addr    : REGISTER_ADDR_T;  
                             rX         : REGISTER_T;
                             rY         : REGISTER_T;
                             rZ         : REGISTER_T;
                             immediate  : IMMEDIATE_T;
                           end record;

  -- bit positions for aluop1
  constant ALUOP1_LD_MEM_BIT : integer := 0;
  constant ALUOP1_ST_MEM_BIT : integer := 1;
  constant ALUOP1_WB_REG_BIT : integer := 2;

  -- bit positions for aluop2
  constant ALUOP2_SR_BIT : integer := 0;
  constant ALUOP2_LR_BIT : integer := 1;

  type EX_MEM_REGISTER_T is record
                              aluop1        : ALUOP1_T;
                              aluop2        : ALUOP2_T;
                              reg           : REGISTER_T;
                              alu           : REGISTER_T;
                              dreg_addr     : REGISTER_ADDR_T;
                              lr            : PC_REGISTER_T;
                              sr            : SR_REGISTER_T;
                            end record;
  
  type MEM_WB_REGISTER_T is record
                              aluop1        : ALUOP1_T;
                              aluop2        : ALUOP2_T;
                              reg           : REGISTER_T;
                              mem_reg       : REGISTER_T;
                              dreg_addr     : REGISTER_ADDR_T;                           
                              lr            : PC_REGISTER_T;
                              sr            : SR_REGISTER_T;
                            end record;
  
    constant CONST_UART_STATUS_ADDRESS: REGISTER_T := x"8000";
	 constant CONST_UART_DATA_ADDRESS: REGISTER_T := x"8001";
end RISE_PACK;

@


1.11
log
@Added address constants for uart access (memory mapped I/O)
@
text
@d19 1
d124 1
a124 1
	  constant CONST_UART_DATA_ADDRESS: REGISTER_T := x"8001";
@


1.10
log
@insert Uart address constant
@
text
@d122 2
a123 3

   constant CONST_ADDRESS: x"8001";

@


1.9
log
@Moved opcode and conditional constants and opcode_t and cond_t data types to rise_const_pack.vhd.
@
text
@d122 3
@


1.8
log
@ - Removed unused constant COND_NONE.
@
text
@d15 1
a24 2
  constant OPCODE_WIDTH : integer := 5;
  constant COND_WIDTH : integer := 3;
a46 2
  subtype OPCODE_T is std_logic_vector(OPCODE_WIDTH-1 downto 0);
  subtype COND_T is std_logic_vector(COND_WIDTH-1 downto 0);
d69 1
a69 43
  -- RISE OPCODES --
  -- load opcodes
  constant OPCODE_LD_IMM        : OPCODE_T := "10000";
  constant OPCODE_LD_IMM_HB     : OPCODE_T := "10010";  
  constant OPCODE_LD_DISP       : OPCODE_T := "10100";
  constant OPCODE_LD_DISP_MS    : OPCODE_T := "11000";
  constant OPCODE_LD_REG        : OPCODE_T := "00001";

  -- store opcodes
  constant OPCODE_ST_DISP       : OPCODE_T := "11100";
  
  -- arithmethic opcodes
  constant OPCODE_ADD           : OPCODE_T := "00010";  
  constant OPCODE_ADD_IMM       : OPCODE_T := "00011";  
  constant OPCODE_SUB           : OPCODE_T := "00100";  
  constant OPCODE_SUB_IMM       : OPCODE_T := "00101";  
  constant OPCODE_NEG           : OPCODE_T := "00110";  
  constant OPCODE_ARS           : OPCODE_T := "00111";  
  constant OPCODE_ALS           : OPCODE_T := "01000";

  -- logical opcodes
  constant OPCODE_AND : OPCODE_T := "01001";
  constant OPCODE_NOT : OPCODE_T := "01010";
  constant OPCODE_EOR : OPCODE_T := "01011";
  constant OPCODE_LS :  OPCODE_T := "01100";
  constant OPCODE_RS :  OPCODE_T := "01101";
  
  -- program control
  constant OPCODE_JMP : OPCODE_T := "01110";

  -- other
  constant OPCODE_TST : OPCODE_T := "01111";
  constant OPCODE_NOP : OPCODE_T := "00000";
  
  -- CONDITION CODES --
  constant COND_UNCONDITIONAL   : COND_T := "000";
  constant COND_NOT_ZERO        : COND_T := "001";
  constant COND_ZERO            : COND_T := "010";
  constant COND_CARRY           : COND_T := "011";
  constant COND_NEGATIVE        : COND_T := "100";
  constant COND_OVERFLOW        : COND_T := "101";
  constant COND_ZERO_NEGATIVE   : COND_T := "110";

@


1.7
log
@ - Added constant for RESET_VECTOR.
@
text
@d67 1
a67 2
  
  constant COND_NONE : COND_T := "000";
@


1.6
log
@- Added seperate memory output vector to MEM_WB_REGISTER.
- Added status register to MEM_WB_REGISTER.
@
text
@d70 3
a72 1
  constant PC_RESET_VECTOR : MEM_ADDR_T := ( others => '0' );
@


1.5
log
@ - Added PC_RESET_VECTOR constant.
@
text
@d46 1
a46 1
    
d155 1
a155 1
    
d160 1
d163 1
@


1.4
log
@ - Added constant definitions for SR, PC and LR register.
@
text
@d70 1
a70 1

@


1.3
log
@Implementation of execute stage and register lock unit. Some changes im RISE package.
@
text
@d55 4
@


1.2
log
@ - correct register address width is 4 bit and not 5 bit.
 - added constants for OPCODES, COND and SR.
@
text
@d14 1
a14 1

d33 3
d51 3
d63 3
a66 1
  constant COND_NONE : COND_T := "000";
d68 31
a98 4
  constant OPCODE_LD_IMM : OPCODE_T := "10000";
  constant OPCODE_LD_DISP : OPCODE_T := "10100";
  constant OPCODE_LD_DISP_MS : OPCODE_T := "11000";
  constant OPCODE_LD_REG : OPCODE_T := "00001";
d100 16
a115 1
    
d132 10
a141 1
  
d143 2
a144 2
                              aluop1        : std_logic_vector(2 downto 0);
                              aluop2        : std_logic_vector(2 downto 0);
d149 1
d153 2
a154 2
                              aluop1        : std_logic_vector(2 downto 0);
                              aluop2        : std_logic_vector(2 downto 0);
@


1.1
log
@Initial commit of project
@
text
@d30 1
a30 1
  constant REGISTER_ADDR_WIDTH : integer := 5;
d48 17
@