head	1.10;
access;
symbols;
locks; strict;
comment	@# @;


1.10
date	2007.01.25.00.25.27;	author ustadler;	state Exp;
branches;
next	1.9;
commitid	29f645b7f8f64567;

1.9
date	2007.01.24.22.03.45;	author jlechner;	state Exp;
branches;
next	1.8;
commitid	64c945b7d7c04567;

1.8
date	2007.01.24.15.34.57;	author trinklhar;	state Exp;
branches;
next	1.7;
commitid	35ad45b77ca04567;

1.7
date	2007.01.24.14.25.14;	author trinklhar;	state Exp;
branches;
next	1.6;
commitid	7fde45b76c494567;

1.6
date	2007.01.14.19.49.36;	author cwalter;	state Exp;
branches;
next	1.5;
commitid	114b45aa894e4567;

1.5
date	2007.01.14.03.20.37;	author jlechner;	state Exp;
branches;
next	1.4;
commitid	335d45a9a1834567;

1.4
date	2007.01.13.23.14.19;	author cwalter;	state Exp;
branches;
next	1.3;
commitid	544e45a967c64567;

1.3
date	2007.01.12.22.59.13;	author jlechner;	state Exp;
branches;
next	1.2;
commitid	43c45a812ba4567;

1.2
date	2007.01.10.03.06.51;	author ustadler;	state Exp;
branches;
next	1.1;
commitid	6abe45a458464567;

1.1
date	2006.12.06.22.41.04;	author jlechner;	state Exp;
branches;
next	;
commitid	6319457746fd4567;


desc
@@


1.10
log
@uart_address_0 was a latch -> changed
@
text
@-- File: dmem.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29

-- Description:
-- Entity for accessing data memory.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

use WORK.RISE_PACK.all;


entity dmem is
  
  port (
    clk   : in std_logic;
    reset : in std_logic;
    wr_enable : in  std_logic;
    addr      : in  MEM_ADDR_T;
    data_in   : in  MEM_DATA_T;
    data_out  : out MEM_DATA_T;
    uart_txd : out std_logic;
    uart_rxd : in std_logic);

end dmem;

architecture dmem_rtl of dmem is

  component idmem
    port (
      addr  : in  std_logic_vector(11 downto 0);
      clk   : in  std_logic;
      din   : in  std_logic_vector(15 downto 0);
      dout  : out std_logic_vector(15 downto 0);
      sinit : in  std_logic;
      we    : in  std_logic);
  end component;
  
  component sc_uart is
                      generic (ADDR_BITS : integer;
                               CLK_FREQ  : integer;
                               BAUD_RATE : integer;
                               TXF_DEPTH : integer;
                               TXF_THRES : integer;
                               RXF_DEPTH : integer;
                               RXF_THRES : integer);
                    port (CLK     : in  std_logic;
                          RESET   : in  std_logic;
                          ADDRESS : in  std_logic_vector(addr_bits-1 downto 0);
                          WR_DATA : in  std_logic_vector(15 downto 0);
                          RD, WR  : in  std_logic;
                          RD_DATA : out std_logic_vector(15 downto 0);
                          RDY_CNT : out unsigned(1 downto 0);
                          TXD     : out std_logic;
                          RXD     : in  std_logic;
                          NCTS    : in  std_logic;
                          NRTS    : out std_logic);
  end component;


  signal uart_address 		: std_logic_vector(1 downto 0);
  signal uart_wr_data 		:std_logic_vector(15 downto 0);
  signal uart_rd 			: std_logic;
  signal uart_wr 			: std_logic;
  signal uart_rd_data		: std_logic_vector(15 downto 0);

  signal uart_txd_sig 		: std_logic;
  signal uart_rxd_sig 		: std_logic;
  
  signal mem_addr : std_logic_vector (11 downto 0);
  signal mem_data_in :MEM_DATA_T;
  signal mem_data_out :MEM_DATA_T;
  signal mem_wr_enable:  std_logic;

  signal last_address_int : MEM_ADDR_T;
  signal last_address_next : MEM_ADDR_T;

  signal rdy_cnt_sig		: IEEE.NUMERIC_STD.unsigned(1 downto 0);
begin  -- dmem_rtl

  -- Uart modul einbinden
  UART : sc_uart generic map (
    ADDR_BITS => 2,
    CLK_FREQ  => CLK_FREQ,
    BAUD_RATE => 115200,
    TXF_DEPTH => 2,
    TXF_THRES => 1,
    RXF_DEPTH => 2,
    RXF_THRES => 1
    )
    port map(
      CLK     => clk,
      RESET   => reset,
      ADDRESS => uart_address(1 downto 0),
      WR_DATA => uart_wr_data,
      RD      => uart_rd,
      WR      => uart_wr,
      RD_DATA => uart_rd_data,
      RDY_CNT => rdy_cnt_sig,
      TXD     => uart_txd_sig,
      RXD     => uart_rxd_sig,
      NCTS    => '0',
      NRTS    => open
      );

  DATA_MEM : idmem
    port map (
      addr  => mem_addr,
      clk   => clk,
      din   => mem_data_in,
      dout  => mem_data_out,
      sinit => reset,
      we    => mem_wr_enable);


  uart_txd 		<= uart_txd_sig;
  uart_rxd_sig          <= uart_rxd;

  store_address: process (clk, reset)
  begin  -- process data_out
    if reset='0' then
      last_address_int <= (others => '0');    
    elsif clk'event and clk='1' then
      last_address_int <= last_address_next;
    end if;
  end process store_address;

  process (last_address_int, mem_data_out, uart_rd_data)
  begin
    if last_address_int = CONST_UART_STATUS_ADDRESS 
      or last_address_int = CONST_UART_DATA_ADDRESS then
      data_out <= uart_rd_data;
    else
      data_out <= mem_data_out;
    end if;
  end process;

  process (wr_enable, addr, data_in, uart_rd_data, mem_data_out)
  begin

    mem_addr <= (others => '0');
    mem_data_in <= (others => '0');
    mem_wr_enable <= '0';
	 uart_address <= (others => '0');

    uart_wr <= '0';
    uart_wr_data <= (others => '0');
    uart_rd <= '0';

    last_address_next <= addr;
    
    if addr = CONST_UART_STATUS_ADDRESS 
      or addr = CONST_UART_DATA_ADDRESS then
      -- accessing UART

      uart_address <= addr (1 downto 0);
      
		if wr_enable = '1' then
        uart_wr <= '1';
        uart_wr_data <= data_in;
      else
        uart_rd <= '1';
      end if;	
    else
      -- accessing data memory
      mem_addr <= addr(11 downto 0);
      mem_data_in <= data_in;
      mem_wr_enable <= wr_enable;
    end if;

  end process;

end dmem_rtl;








@


1.9
log
@Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.
@
text
@d148 1
d161 2
a162 1
      if wr_enable = '1' then
@


1.8
log
@Fixed vhdl bugs
@
text
@d26 2
a27 2
	 uart_txd : out std_logic;
	 uart_rxd : in std_logic);
d43 40
a82 37
   component sc_uart is
      generic (ADDR_BITS : integer;
               CLK_FREQ  : integer;
               BAUD_RATE : integer;
               TXF_DEPTH : integer;
               TXF_THRES : integer;
               RXF_DEPTH : integer;
               RXF_THRES : integer);
      port (CLK     : in  std_logic;
            RESET   : in  std_logic;
            ADDRESS : in  std_logic_vector(addr_bits-1 downto 0);
            WR_DATA : in  std_logic_vector(15 downto 0);
            RD, WR  : in  std_logic;
            RD_DATA : out std_logic_vector(15 downto 0);
            RDY_CNT : out unsigned(1 downto 0);
            TXD     : out std_logic;
            RXD     : in  std_logic;
            NCTS    : in  std_logic;
            NRTS    : out std_logic);
    end component;


     signal uart_address 		: std_logic_vector(1 downto 0);
      signal uart_wr_data 		:std_logic_vector(15 downto 0);
      signal uart_rd 			: std_logic;
      signal uart_wr 			: std_logic;
      signal uart_rd_data		: std_logic_vector(15 downto 0);

      signal uart_txd_sig 		: std_logic;
      signal uart_rxd_sig 		: std_logic;
		
		signal mem_addr : std_logic_vector (11 downto 0);
		signal mem_data_in :MEM_DATA_T;
      signal mem_data_out :MEM_DATA_T;
      signal mem_wr_enable:  std_logic;
		
		signal rdy_cnt_sig		: IEEE.NUMERIC_STD.unsigned(1 downto 0);
d95 1
a95 1
	 port map(
d120 2
a121 7
uart_txd 		<= uart_txd_sig;
uart_rxd_sig 	<= uart_rxd;

process (wr_enable, addr, data_in, uart_rd_data, mem_data_out)
begin


d123 49
a171 18
-- accessing extension modules
if addr = CONST_UART_STATUS_ADDRESS 
	or addr = CONST_UART_DATA_ADDRESS then
	uart_address <= addr (1 downto 0);
	if wr_enable = '1' then
		uart_wr <= '1';
		uart_wr_data <= data_in;
	else
		uart_rd <= '1';
		data_out <= uart_rd_data;		
	end if;	
else
	-- accessing data memory
	mem_addr <= addr(11 downto 0);
	data_out <= mem_data_out;
	mem_data_in <= data_in;
	mem_wr_enable <= wr_enable;
end if;
d173 1
a173 1
end process;
@


1.7
log
@Added UART module to memory entity
@
text
@d12 1
a12 1
use IEEE.STD_LOGIC_ARITH.all;
a21 1

d42 1
d57 1
a57 1
            RDY_CNT : out IEEE.NUMERIC_STD.unsigned(1 downto 0);
d65 5
a69 5
     signal uart_address(1 downto 0): std_logic_vector(1 downto 0);
      signal uart_wr_data :std_logic_vector(15 downto 0);
      signal uart_rd : std_logic;
      signal uart_wr : std_logic;
      signal uart_rd_data: std_logic_vector(15 downto 0);
d71 2
a72 2
      signal uart_txd_sig : std_logic;
      signal uart_rxd_sig : std_logic;
d78 2
d100 1
a100 1
      RDY_CNT => open,
d117 2
a118 2
uart_txd <= uart_txd_sig;
uart_rxd <= uart_rxd_sig;
d144 1
a144 1
end process
@


1.6
log
@ - Applied indenting tool.
@
text
@d26 3
a28 1
    data_out  : out MEM_DATA_T);
d43 36
d80 24
a103 1
begin  -- dmem_rtl
d107 1
a107 1
      addr  => addr(11 downto 0),
d109 2
a110 2
      din   => data_in,
      dout  => data_out,
d112 29
a140 1
      we    => wr_enable);
d142 1
@


1.5
log
@Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation
@
text
@d12 1
a12 1
use IEEE.NUMERIC_STD.all;
d15 1
a15 1
use work.RISE_PACK_SPECIFIC.all;
d20 3
a22 2
    clk       : in  std_logic;
    reset     : in  std_logic;
d31 1
d43 1
d52 2
@


1.4
log
@ - Applied indenting tool.
@
text
@d15 1
a15 1

@


1.3
log
@Applied VHDL indent.
@
text
@a0 1

d12 1
a12 1
use IEEE.STD_LOGIC_ARITH.all;
d20 6
a25 6
    clk            : in std_logic;
    reset          : in std_logic;
    wr_enable	   : in std_logic;
    addr           : in MEM_ADDR_T;
    data_in        : in MEM_DATA_T;
    data_out       : out MEM_DATA_T);
a29 1

d32 6
a37 6
      addr: IN std_logic_VECTOR(11 downto 0);
      clk: IN std_logic;
      din: IN std_logic_VECTOR(15 downto 0);
      dout: OUT std_logic_VECTOR(15 downto 0);
      sinit: IN std_logic;
      we: IN std_logic);
a40 1

d43 4
a46 4
      addr => addr(11 downto 0),
      clk => clk,
      din => data_in,
      dout => data_out,
d48 1
a48 3
      we => wr_enable);
  

@


1.2
log
@4k Data Memory for Spartan 3 (Block RAM)
Added write enable to the entity
@
text
@d23 1
a23 2

    wr_enable		 : in std_logic;
d32 9
a40 9
component idmem
	port (
	addr: IN std_logic_VECTOR(11 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(15 downto 0);
	dout: OUT std_logic_VECTOR(15 downto 0);
	sinit: IN std_logic;
	we: IN std_logic);
end component;
d44 8
a51 8
DATA_MEM : idmem
	port map (
	addr => addr(11 downto 0),
	clk => clk,
	din => data_in,
	dout => data_out,
	sinit => reset,
	we => wr_enable);
@


1.1
log
@Initial commit of project
@
text
@d1 1
d24 1
d33 10
d45 8
d56 8
@