head	1.1;
access;
symbols;
locks; strict;
comment	@# @;


1.1
date	2007.02.07.08.09.19;	author jcarr;	state Exp;
branches;
next	;
commitid	3c1b45c989214567;


desc
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1.1
log
@adding the source directory
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text
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	)
	port map (

	    clk_i   	=> clk33,
   		nrst_i  	=> nrst,
		--
		adr_i		=> adr(7 downto 2),
		cbe_i		=> cbe,
		dat_i		=> pcidatwrite,
		dat_o		=> pcidatread,
   		wrcfg_i     => wrcfg,
   		rdcfg_i     => rdcfg,
   		perr_i      => parerr,
   		serr_i      => syserr,
   		tabort_i    => tabort,
		bar0_o		=> bar0,
		perrEN_o	=> perrEN,
		serrEN_o	=> serrEN,
		memEN_o		=> memEN
					
	);
	
	--+-----------------------------------------+
	--|  PCI Parity Gnerator					|
	--+-----------------------------------------+

	u5: component pcipargen
	port map (

	    clk_i   	=> clk33,
		pcidatout_i	=> pcidatout,	
		cbe_i		=> cbe,
		parOE_i		=> parOE,	
		par_o		=> par
					
	);


	--+-----------------------------------------+
	--|  Whisbone Address bus					|
	--+-----------------------------------------+
	
	wb_adr_o <= adr;


	--+-----------------------------------------+
	--|  unimplemented							|
	--+-----------------------------------------+

	parerr 	<= '0';
	syserr 	<= '0';
	tabort 	<= '0';


	--+-----------------------------------------+
	--|  unused outputs							|
	--+-----------------------------------------+
	-- #stop: Curret TARGET indicates to Master stop current transaction
	-- #perr:
	-- #serr:
	
	perr 	<= 'Z';
	serr	<= 'Z';
	stop	<= 'Z';
	intb	<= '0' when ( wb_int_i = '1' ) else 'Z';

		
end rtl;


@