head	1.1;
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symbols;
locks; strict;
comment	@# @;


1.1
date	2007.02.07.08.09.19;	author jcarr;	state Exp;
branches;
next	;
commitid	3c1b45c989214567;


desc
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1.1
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	);
	port (
	
	    clk_i       	: in std_logic;
   		nrst_i       	: in std_logic;
		--
		adr_i			: in std_logic_vector(7 downto 2);
		cbe_i			: in std_logic_vector(3 downto 0);
		dat_i			: in std_logic_vector(31 downto 0);
		dat_o			: out std_logic_vector(31 downto 0);
   		wrcfg_i       	: in std_logic;
   		rdcfg_i       	: in std_logic;
   		perr_i       	: in std_logic;
   		serr_i       	: in std_logic;
   		tabort_i       	: in std_logic;
		bar0_o			: out std_logic_vector(31 downto 25);
		perrEN_o		: out std_logic;
		serrEN_o		: out std_logic;
		memEN_o			: out std_logic
				
	);
	end component;


	component pcipargen
	port (

		clk_i			: in std_logic;
		pcidatout_i		: in std_logic_vector(31 downto 0);
		cbe_i			: in std_logic_vector(3 downto 0);
		parOE_i 		: in std_logic;
		par_o			: out std_logic
	
	);   
	end component;


--+-----------------------------------------------------------------------------+
--|									CONSTANTS  									|
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--|									SIGNALS   									|
--+-----------------------------------------------------------------------------+

	signal bar0			: std_logic_vector(31 downto 25);
	signal memEN		: std_logic;
	signal pciadrLD		: std_logic;
	signal adrcfg		: std_logic;
	signal adrmem		: std_logic;
	signal adr			: std_logic_vector(24 downto 1);
	signal cmd			: std_logic_vector(3 downto 0);
	signal pcidOE		: std_logic;
	signal parOE		: std_logic;	
	signal wbdatLD		: std_logic;
	signal wbrgdMX		: std_logic;
	signal wbd16MX		: std_logic;
	signal wrcfg		: std_logic;
	signal rdcfg		: std_logic;
	signal pcidatread	: std_logic_vector(31 downto 0);
	signal pcidatwrite	: std_logic_vector(31 downto 0);
	signal pcidatout	: std_logic_vector(31 downto 0);	
	signal parerr		: std_logic;
	signal syserr		: std_logic;
	signal tabort		: std_logic;
	signal perrEN		: std_logic;
	signal serrEN		: std_logic;
			
begin


    --+-------------------------------------------------------------------------+
    --|  Component instances													|
    --+-------------------------------------------------------------------------+

	--+-----------------------------------------+
	--|  PCI decoder							|
	--+-----------------------------------------+

	u1: component pcidec_new
	port map (

	    clk_i   	=> clk33,
   		nrst_i 		=> nrst,
		--
		ad_i		=> ad,
		cbe_i		=> cbe,
		idsel_i    	=> idsel,
		bar0_i      => bar0,
		memEN_i		=> memEN,
		pciadrLD_i	=> pciadrLD,	
		adrcfg_o	=> adrcfg,
		adrmem_o	=> adrmem,
		adr_o		=> adr,
		cmd_o		=> cmd
		
	);


	--+-----------------------------------------+
	--|  PCI-WB Sequencer						|
	--+-----------------------------------------+

	u2: component pciwbsequ 
	port map (

   		-- General 
	    clk_i 		=> clk33,     	
   		nrst_i      => nrst,
		-- pci 
		cmd_i			=> cmd,
		cbe_i			=> cbe,
		frame_i    		=> frame,
		irdy_i      	=> irdy,	
		devsel_o		=> devsel,
		trdy_o      	=> trdy, 	
		-- control
		adrcfg_i		=> adrcfg,
		adrmem_i 		=> adrmem,
		pciadrLD_o		=> pciadrLD,
		pcidOE_o		=> pcidOE,
		parOE_o			=> parOE,    
		wbdatLD_o   	=> wbdatLD,
		wbrgdMX_o		=> wbrgdMX,
		wbd16MX_o		=> wbd16MX,
		wrcfg_o 		=> wrcfg,
		rdcfg_o 		=> rdcfg,
		-- whisbone
		wb_sel_o		=> wb_sel_o,
		wb_we_o			=> wb_we_o,
		wb_stb_o		=> wb_stb_o,
		wb_cyc_o		=> wb_cyc_o,
		wb_ack_i		=> wb_ack_i,
		wb_err_i		=> wb_err_i,
		-- debug signals
		debug_init		=> debug_init, 
		debug_access 	=> debug_access
	);
   

	--+-----------------------------------------+
	--|  PCI-wb datamultiplexer					|
	--+-----------------------------------------+

	u3: component pcidmux
	port map (

	    clk_i   	=> clk33,
   		nrst_i  	=> nrst,
		--
		d_io		=> ad,	
		pcidatout_o	=> pcidatout,	
		pcidOE_i	=> pcidOE,
		wbdatLD_i	=> wbdatLD,
		wbrgdMX_i	=> wbrgdMX,
		wbd16MX_i	=> wbd16MX,
		wb_dat_i	=> wb_dat_i,
		wb_dat_o	=> wb_dat_o,
		rg_dat_i	=> pcidatread,
		rg_dat_o	=> pcidatwrite
			
	);


	--+-----------------------------------------+
	--|  PCI registers							|
	--+-----------------------------------------+

	u4: component pciregs
	generic map (

		vendorID 		=> vendorID,
		deviceID 		=> deviceID,
		revisionID 		=> revisionID,
		subsystemID 	=> subsystemID,
    	subsystemvID 	=> subsystemvID,
@