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1.1
date	2007.02.07.08.09.19;	author jcarr;	state Exp;
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commitid	3c1b45c989214567;


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1.1
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@--+-------------------------------------------------------------------------------------------------+
--|																									|
--|  File:			pci32tlite.vhd                       		                                   	|
--|																									|
--|  Components:	pcidec_new.vhd																		|
--|		            pciwbsequ.vhd           														|
--|		            pcidmux.vhd           															|
--|		            pciregs.vhd           															|
--|		            pcipargen.vhd          															|
--|		            -- Libs --             															|
--|		            ona.vhd		          															|
--|																									|
--|	 Description:	TARGET PCI :						 							|
--| 				 																				|
--|					* PCI Target 32 Bits															|
--|					* BAR0 32MByte address space													|
--|					* Whisbone compatible: D16, 32MB address space                                  |
--|																									|
--+-------------------------------------------------------------------------------------------------+
--|																									|
--|  Revision history :																				|
--|  Date 		  Version	Author	Description														|
--|  2005-05-13   R00A00	PAU		First alfa revision (eng)										|
--|	 2006-01-05   R00B00    MS      inverted reset nres 											|
--|                                 and added debug signals debug_init and debug_access             |																								|
--|																									|
--|  To do:																 							|
--|																									|
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| 																|
--|  Copyright (C) 2005 Peio Azkarate, peio@@opencores.org   		| 
--| 																|
--|  This source file may be used and distributed without     		|
--|  restriction provided that this copyright statement is not		|
--|  removed from the file and that any derivative work contains	|
--|  the original copyright notice and the associated disclaimer.	|
--|                                                              	|
--|  This source file is free software; you can redistribute it     |
--|  and/or modify it under the terms of the GNU Lesser General     |
--|  Public License as published by the Free Software Foundation;   |
--|  either version 2.1 of the License, or (at your option) any     |
--|  later version.                                                 |
--| 																|
--|  This source is distributed in the hope that it will be         |
--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |
--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |
--|  PURPOSE.  See the GNU Lesser General Public License for more   |
--|  details.                                                       |
--| 																|
--|  You should have received a copy of the GNU Lesser General      |
--|  Public License along with this source; if not, download it     |
--|  from http://www.opencores.org/lgpl.shtml                       |
--| 																|
--+-----------------------------------------------------------------+ 

--+-----------------------------------------------------------------------------+
--|									LIBRARIES									|
--+-----------------------------------------------------------------------------+

library ieee;
use ieee.std_logic_1164.all;

--+-----------------------------------------------------------------------------+
--|									ENTITY   									|
--+-----------------------------------------------------------------------------+

entity pci32tlite is
generic (

	vendorID 		: std_logic_vector(15 downto 0) := x"10EE";
	deviceID 		: std_logic_vector(15 downto 0) := x"0100";
	revisionID 		: std_logic_vector(7 downto 0) 	:= x"37";
	subsystemID 	: std_logic_vector(15 downto 0) := x"1558";
   	subsystemvID 	: std_logic_vector(15 downto 0) := x"0480";
@