head	1.3;
access;
symbols
	rel_15:1.3
	rel_14:1.2
	rel_13:1.1;
locks; strict;
comment	@# @;


1.3
date	2003.12.09.11.24.02;	author gorand;	state Exp;
branches;
next	1.2;

1.2
date	2003.12.01.14.46.55;	author gorand;	state Exp;
branches;
next	1.1;

1.1
date	2003.11.30.11.55.00;	author gorand;	state Exp;
branches;
next	;


desc
@@


1.3
log
@modified by simulation.
@
text
@TOOL:	ncelab	04.10-b001: Started on Dec 09, 2003 at 12:26:38
ncelab
    -f ncelab.args
        -MESSAGES
        -NOCOPYRIGHT
        -CDSLIB ../bin/cds.lib
        -HDLVAR ../bin/hdl.var
        -LOGFILE ../log/ncelab.log
        -TIMESCALE 1ns/100ps
        -SNAPSHOT worklib.ps2_test_bench:rtl
        -NO_TCHK_MSG
        -ACCESS +RWC
        worklib.ps2_test_bench

	Elaborating the design hierarchy:
		Caching library 'worklib' ....... Done
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.WB_MASTER32:v <0x285dcd5e>
			streams:  14, words: 37673
		worklib.WB_MASTER_BEHAVIORAL:v <0x4011829a>
			streams:   6, words: 64972
		worklib.ps2_io_ctrl:v <0x1a9cfb7e>
			streams:   7, words:  4237
		worklib.ps2_keyboard:v <0x48cda7c5>
			streams: 107, words: 77889
		worklib.ps2_keyboard_model:v <0x64c1328f>
			streams:  13, words: 19418
		worklib.ps2_sim_top:v <0x3261324c>
			streams:   4, words:  1087
		worklib.ps2_test_bench:v <0x1e73bec9>
			streams:  46, words: 159235
		worklib.ps2_top:v <0x758f909c>
			streams:   3, words:   782
		worklib.ps2_translation_table:v <0x726febd5>
			streams:  14, words:  9671
		worklib.ps2_wb_if:v <0x2138f2f1>
			streams: 101, words: 78860
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		                 Instances  Unique
		Modules:                10      10
		Primitives:              2       1
		Registers:             254     254
		Scalar wires:           74       -
		Expanded wires:         32       1
		Vectored wires:         16       -
		Always blocks:          41      41
		Initial blocks:          4       4
		Parallel blocks:        14      14
		Cont. assignments:      40      56
		Pseudo assignments:      5      59
		Simulation timescale:  1ps
	Writing initial simulation snapshot: worklib.ps2_test_bench:rtl
TOOL:	ncelab	04.10-b001: Exiting on Dec 09, 2003 at 12:26:40  (total: 00:00:02)
@


1.2
log
@small changes, for VATS... ( boring ) :)
@
text
@d1 1
a1 1
TOOL:	ncelab	04.10-b001: Started on Dec 01, 2003 at 15:50:29
d56 1
a56 1
TOOL:	ncelab	04.10-b001: Exiting on Dec 01, 2003 at 15:50:32  (total: 00:00:03)
@


1.1
log
@added
@
text
@d1 1
a1 1
TOOL:	ncelab	04.10-b001: Started on Nov 30, 2003 at 12:53:31
d56 1
a56 1
TOOL:	ncelab	04.10-b001: Exiting on Nov 30, 2003 at 12:53:33  (total: 00:00:02)
@