head	1.4;
access;
symbols
	ver_tag:1.1.1.1 vendor_tag:1.1.1;
locks; strict;
comment	@# @;


1.4
date	2008.07.03.16.26.30;	author dimo;	state Exp;
branches;
next	1.3;
commitid	1524486cfda64567;

1.3
date	2008.07.02.15.12.22;	author dimo;	state Exp;
branches;
next	1.2;
commitid	2320486b9acf4567;

1.2
date	2008.06.27.17.41.49;	author dimo;	state Exp;
branches;
next	1.1;
commitid	7a08486526444567;

1.1
date	2008.06.23.19.58.00;	author dimo;	state Exp;
branches
	1.1.1.1;
next	;
commitid	1b3f4860003f4567;

1.1.1.1
date	2008.06.23.19.58.00;	author dimo;	state Exp;
branches;
next	;
commitid	1b3f4860003f4567;


desc
@@


1.4
log
@testbench havior fixed
@
text
@library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu_types.all;

entity ram_control is
  port( clk,rst : in std_logic;
        input_a : IN d_bus;
        input_rom : IN d_bus;
        input_ram : in d_bus;
        control : in opcode;
        ram_data_reg : out d_bus;
        addr : OUT d_bus;
        data : OUT d_bus;
        ce_nwr, ce_nrd : OUT STD_LOGIC );
end ram_control;


architecture behavioral of ram_control is
  signal n_clk, p_clk : std_logic;
begin
  addr <= input_rom;
  data <= input_a;
  
n_sig: process(clk)
begin
  if clk'event and clk='0' then
    if rst='1' then
      n_clk <= '0';    
    else
      n_clk <= not n_clk;
    end if;
  end if;
end process;

p_sig: process(clk)
begin
  if clk'event and clk='1' then
      p_clk <= n_clk;
  end if;
end process;

wr_p: process(p_clk,n_clk,control)
begin
  if control=sta_1 then
    ce_nwr <= not p_clk xor n_clk;
  else
    ce_nwr <= '1';
  end if;
end process;


----rd_p: process(clk,control)
----begin
----  if control=lda_addr_1 or control=ldb_addr_1 then
----    ce_nrd <= clk;
----  else
----    ce_nrd <= '1';
----  end if;
----end process;


rd_p: process(p_clk,n_clk,control)
BEGIN
  IF control=lda_addr_1 OR control=ldb_addr_1 then
    ce_nrd <= not p_clk xor n_clk;
  else
    ce_nrd <= '1';
  end if;
END process;

ram_data: process(clk)
begin
  if clk'event and clk='1' then
    if control=lda_addr_1 or control=ldb_addr_1 then
      ram_data_reg <= input_ram;
    end if;
  end if;
end process;

----ram_addr: process(clk)
----begin
----  if clk'event and clk='0' then
----    if rst='1' then
----      ram_addr_reg <= zero_bus;
----    else
----      if control=sta_1 then
----        ram_addr_reg <= input_rom;
----      end if;
----   end if;
----  end if;
----end process;
END behavioral;
@


1.3
log
@updated
@
text
@d20 1
a20 2
  signal pr_state, nxt_state : opcode;
--  signal ram_addr_reg : d_bus;
a21 2

--  addr <= ram_addr_reg;
d25 19
a43 1
wr_p: process(clk,control)
d46 1
a46 1
    ce_nwr <= clk;
d53 8
a60 8
--rd_p: process(clk,control)
--begin
--  if control=lda_addr_1 or control=ldb_addr_1 then
--    ce_nrd <= clk;
--  else
--    ce_nrd <= '1';
--  end if;
--end process;
d63 1
a63 1
rd_p: process(clk,control)
d66 1
a66 1
    ce_nrd <= clk;
d81 12
a92 12
--ram_addr: process(clk)
--begin
--  if clk'event and clk='0' then
--    if rst='1' then
--      ram_addr_reg <= zero_bus;
--    else
--      if control=sta_1 then
--        ram_addr_reg <= input_rom;
--      end if;
--    end if;
--  end if;
--end process;
@


1.2
log
@control unit bus fixed
ram_control block improved
@
text
@d48 1
a48 1
rd_p: process(clk)
@


1.1
log
@Initial revision
@
text
@d50 5
a54 7
  IF clk'EVENT AND clk='1' THEN
    IF control=lda_addr_1 OR control=ldb_addr_1 then
      ce_nrd <= '0';
    ELSE
      ce_nrd <= '1';
    END IF;
  END IF;
d60 1
a60 1
    if control=lda_addr_2 or control=ldb_addr_2 then
@


1.1.1.1
log
@first upload
@
text
@@