head	1.5;
access;
symbols
	bg2_23:1.5
	bg2_22:1.5
	bg2_21:1.5
	bg2_20:1.5
	bg2_16:1.5
	bg2_15:1.5
	bg2_12:1.5
	bg2_07:1.5
	isorc2008_submission:1.4
	handbook_alpha_edition:1.4
	jtres2007_submission:1.4;
locks; strict;
comment	@# @;


1.5
date	2008.03.03.09.44.59;	author martin;	state Exp;
branches;
next	1.4;
commitid	47947cbc8994567;

1.4
date	2007.06.08.12.41.51;	author martin;	state Exp;
branches;
next	1.3;
commitid	3af546694e8a4567;

1.3
date	2007.03.21.19.48.56;	author martin;	state Exp;
branches;
next	1.2;
commitid	4f8046018c274567;

1.2
date	2007.03.21.19.18.19;	author martin;	state Exp;
branches;
next	1.1;
commitid	36cf460184fa4567;

1.1
date	2007.03.21.19.14.27;	author martin;	state Exp;
branches;
next	;
commitid	323d460184114567;


desc
@@


1.5
log
@added scratchpad RAM
@
text
@JDF G
// Created by Project Navigator ver 1.0
PROJECT jop
DESIGN jop
DEVFAM virtex4
DEVFAMTIME 0
DEVICE xc4vlx25
DEVICETIME 0
DEVPKG ff668
DEVPKGTIME 0
DEVSPEED -10
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\..\vhdl\top\jop_config_ml401.vhd
SOURCE ..\..\vhdl\core\jop_types.vhd
SOURCE ..\..\vhdl\simpcon\sc_pack.vhd
SOURCE ..\..\vhdl\scio\fifo.vhd
SOURCE ..\..\vhdl\scio\sc_uart.vhd
SOURCE ..\..\vhdl\scio\sc_sys.vhd
SOURCE ..\..\vhdl\scio\scio_min.vhd
SOURCE ..\..\vhdl\core\extension.vhd
SOURCE ..\..\vhdl\core\bcfetch.vhd
SOURCE ..\..\vhdl\core\fetch.vhd
SOURCE ..\..\vhdl\core\shift.vhd
SOURCE ..\..\vhdl\core\cache.vhd
SOURCE ..\..\vhdl\xilinx\xs3_jbc.vhd
SOURCE ..\..\vhdl\memory\mem_sc.vhd
SOURCE ..\..\vhdl\memory\sdpram.vhd
SOURCE ..\..\vhdl\memory\sc_sram32.vhd
SOURCE ..\..\vhdl\core\stack.vhd
SOURCE ..\..\vhdl\core\mul.vhd
SOURCE ..\..\vhdl\core\core.vhd
SOURCE ..\..\vhdl\core\decode.vhd
SOURCE ..\..\vhdl\jtbl.vhd
SOURCE ..\..\vhdl\offtbl.vhd
SOURCE ..\..\vhdl\rom.vhd
SOURCE ..\..\vhdl\xilinx\xram.vhd
SOURCE ..\..\vhdl\xv4ram_block.vhd
SOURCE ..\..\vhdl\core\jopcpu.vhd
SOURCE ..\..\vhdl\top\jop_ml401.vhd
DEPASSOC jop jop.ucf
@


1.4
log
@use sc_sys instead of sc_cnt
@
text
@d34 1
@


1.3
log
@Xilinx ML401 board
@
text
@d25 1
a25 1
SOURCE ..\..\vhdl\scio\sc_cnt.vhd
@


1.2
log
@Xilinx ML401 board
@
text
@d46 1
a46 1
DEPASSOC jop jop_ml401.ucf
@


1.1
log
@Xilinx ML401 board
@
text
@d5 1
a5 1
DEVFAM spartan3
d7 1
a7 1
DEVICE xc3s200
d9 1
a9 1
DEVPKG ft256
d11 1
a11 2
DEVSPEED -5
DEVSPEEDTIME 1097243223
@