head	1.21;
access;
symbols
	bg2_23:1.21
	bg2_22:1.21
	bg2_21:1.21
	bg2_20:1.21
	bg2_16:1.21
	bg2_15:1.21
	bg2_12:1.21
	bg2_07:1.21
	isorc2008_submission:1.15
	handbook_alpha_edition:1.14
	jtres2007_submission:1.14
	bg1_07:1.12
	bg1_06:1.12
	bg1_05:1.12
	TAL_101:1.12
	TAL_100:1.12
	jtres_submission:1.12
	wises06_submission:1.12
	lctes2006_submission:1.12
	rtgc_isorc2006:1.9.0.4
	isorc2006:1.9.0.2
	rtgc_paper:1.9
	bg1_00:1.6
	nohandle:1.5
	thesis:1.3;
locks; strict;
comment	@# @;


1.21
date	2008.03.04.19.32.58;	author martin;	state Exp;
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1.20
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1.19
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1.18
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date	2005.05.11.16.18.28;	author martin;	state Exp;
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date	2005.02.05.17.02.50;	author martin;	state Exp;
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1.2
date	2004.09.13.08.34.08;	author martin;	state Exp;
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1.1
date	2004.09.10.08.24.46;	author martin;	state Exp;
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next	;


desc
@@


1.21
log
@add scratchpad RAM configuration to the top-level
@
text
@--
--
--  This file is a part of JOP, the Java Optimized Processor
--
--  Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--


--
--	jopcyc12.vhd
--
--	top level for cycore borad with EP1C12
--
--	2002-03-28	creation
--	2002-06-27	isa bus for CS8900
--	2002-07-27	io for baseio
--	2002-08-02	second uart (use first for download and debug)
--	2002-11-01	removed second uart
--	2002-12-01	split memio
--	2002-12-07	disable clkout
--	2003-02-21	adapt for new Cyclone board with EP1C6
--	2003-07-08	invertion of cts, rts to uart
--	2004-09-11	new extension module
--	2004-10-08	mul operands from a and b, single instruction
--	2005-05-12	added the bsy routing through extension
--	2005-08-15	sp_ov can be used to show a stoack overflow on the wd pin
--	2005-11-30	SimpCon for IO devices
--	2007-03-17	Use jopcpu and change component interface to records
--
--


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.jop_types.all;
use work.sc_pack.all;
use work.jop_config.all;


entity jop is

generic (
	ram_cnt		: integer := 2;		-- clock cycles for external ram
--	rom_cnt		: integer := 3;		-- clock cycles for external rom OK for 20 MHz
	rom_cnt		: integer := 15;	-- clock cycles for external rom for 100 MHz
	jpc_width	: integer := 12;	-- address bits of java bytecode pc = cache size
	block_bits	: integer := 4;		-- 2*block_bits is number of cache blocks
	spm_width	: integer := 0		-- size of scratchpad RAM (in number of address bits for 32-bit words)
);

port (
	clk		: in std_logic;
--
--	serial interface
--
	ser_txd			: out std_logic;
	ser_rxd			: in std_logic;
	ser_ncts		: in std_logic;
	ser_nrts		: out std_logic;

--
--	watchdog
--
	wd		: out std_logic;
	freeio	: out std_logic;

--
--	two ram banks
--
	rama_a		: out std_logic_vector(17 downto 0);
	rama_d		: inout std_logic_vector(15 downto 0);
	rama_ncs	: out std_logic;
	rama_noe	: out std_logic;
	rama_nlb	: out std_logic;
	rama_nub	: out std_logic;
	rama_nwe	: out std_logic;
	ramb_a		: out std_logic_vector(17 downto 0);
	ramb_d		: inout std_logic_vector(15 downto 0);
	ramb_ncs	: out std_logic;
	ramb_noe	: out std_logic;
	ramb_nlb	: out std_logic;
	ramb_nub	: out std_logic;
	ramb_nwe	: out std_logic;

--
--	config/program flash and big nand flash
--
	fl_a	: out std_logic_vector(18 downto 0);
	fl_d	: inout std_logic_vector(7 downto 0);
	fl_ncs	: out std_logic;
	fl_ncsb	: out std_logic;
	fl_noe	: out std_logic;
	fl_nwe	: out std_logic;
	fl_rdy	: in std_logic;

--
--	I/O pins of board
--
	io_b	: inout std_logic_vector(10 downto 1);
	io_l	: inout std_logic_vector(20 downto 1);
	io_r	: inout std_logic_vector(20 downto 1);
	io_t	: inout std_logic_vector(6 downto 1)
);
end jop;

architecture rtl of jop is

--
--	components:
--

component pll is
generic (multiply_by : natural; divide_by : natural);
port (
	inclk0		: in std_logic;
	c0			: out std_logic
);
end component;

--
--	Signals
--
	signal clk_int			: std_logic;

	signal int_res			: std_logic;
	signal res_cnt			: unsigned(2 downto 0) := "000";	-- for the simulation

	attribute altera_attribute : string;
	attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";

--
--	jopcpu connections
--
	signal sc_mem_out		: sc_out_type;
	signal sc_mem_in		: sc_in_type;
	signal sc_io_out		: sc_out_type;
	signal sc_io_in			: sc_in_type;
	signal irq_in			: irq_bcf_type;
	signal irq_out			: irq_ack_type;
	signal exc_req			: exception_type;

--
--	IO interface
--
	signal ser_in			: ser_in_type;
	signal ser_out			: ser_out_type;
	signal wd_out			: std_logic;

	-- for generation of internal reset

-- memory interface

	signal ram_addr			: std_logic_vector(17 downto 0);
	signal ram_dout			: std_logic_vector(31 downto 0);
	signal ram_din			: std_logic_vector(31 downto 0);
	signal ram_dout_en		: std_logic;
	signal ram_ncs			: std_logic;
	signal ram_noe			: std_logic;
	signal ram_nwe			: std_logic;
	
-- remove the comment for RAM access counting
-- signal ram_count		: std_logic;


begin

--
--	intern reset
--	no extern reset, epm7064 has too less pins
--

process(clk_int)
begin
	if rising_edge(clk_int) then
		if (res_cnt/="111") then
			res_cnt <= res_cnt+1;
		end if;

		int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
	end if;
end process;

--
--	components of jop
--
	pll_inst : pll generic map(
		multiply_by => pll_mult,
		divide_by => pll_div
	)
	port map (
		inclk0	 => clk,
		c0	 => clk_int
	);
-- clk_int <= clk;

	wd <= wd_out;

	cpm_cpu: entity work.jopcpu
		generic map(
			jpc_width => jpc_width,
			block_bits => block_bits,
			spm_width => spm_width
		)
		port map(clk_int, int_res,
			sc_mem_out, sc_mem_in,
			sc_io_out, sc_io_in,
			irq_in, irq_out, exc_req);

	cmp_io: entity work.scio 
		port map (clk_int, int_res,
			sc_io_out, sc_io_in,
			irq_in, irq_out, exc_req,

			txd => ser_txd,
			rxd => ser_rxd,
			ncts => ser_ncts,
			nrts => ser_nrts,
			wd => wd_out,
			l => io_l,
			r => io_r,
			t => io_t,
			b => io_b
			-- remove the comment for RAM access counting
			-- ram_cnt => ram_count
		);

	cmp_scm: entity work.sc_mem_if
		generic map (
			ram_ws => ram_cnt-1,
			rom_ws => rom_cnt-1
		)
		port map (clk_int, int_res,
			sc_mem_out, sc_mem_in,

			ram_addr => ram_addr,
			ram_dout => ram_dout,
			ram_din => ram_din,
			ram_dout_en	=> ram_dout_en,
			ram_ncs => ram_ncs,
			ram_noe => ram_noe,
			ram_nwe => ram_nwe,

			fl_a => fl_a,
			fl_d => fl_d,
			fl_ncs => fl_ncs,
			fl_ncsb => fl_ncsb,
			fl_noe => fl_noe,
			fl_nwe => fl_nwe,
			fl_rdy => fl_rdy

		);

	process(ram_dout_en, ram_dout)
	begin
		if ram_dout_en='1' then
			rama_d <= ram_dout(15 downto 0);
			ramb_d <= ram_dout(31 downto 16);
		else
			rama_d <= (others => 'Z');
			ramb_d <= (others => 'Z');
		end if;
	end process;

	ram_din <= ramb_d & rama_d;
	
-- remove the comment for RAM access counting
-- ram_count <= ram_ncs;


--
--	To put this RAM address in an output register
--	we have to make an assignment (FAST_OUTPUT_REGISTER)
--
	rama_a <= ram_addr;
	rama_ncs <= ram_ncs;
	rama_noe <= ram_noe;
	rama_nwe <= ram_nwe;
	rama_nlb <= '0';
	rama_nub <= '0';

	ramb_a <= ram_addr;
	ramb_ncs <= ram_ncs;
	ramb_noe <= ram_noe;
	ramb_nwe <= ram_nwe;
	ramb_nlb <= '0';
	ramb_nub <= '0';

	freeio <= 'Z';

end rtl;
@


1.20
log
@JOP goes GPL
@
text
@d62 2
a63 1
	block_bits	: integer := 4		-- 2*block_bits is number of cache blocks
d216 2
a217 1
			block_bits => block_bits
d305 1
a305 1
end rtl;@


1.19
log
@no message
@
text
@d2 21
@


1.18
log
@no message
@
text
@a128 1
	signal atomic				: std_logic;
@


1.17
log
@Cleanup of SimpCon types
@
text
@d129 1
@


1.16
log
@Memory access counter included
@
text
@d127 1
a127 1
	signal sc_mem_out		: sc_mem_out_type;
d129 1
a129 1
	signal sc_io_out		: sc_io_out_type;
@


1.15
log
@additional signal from bcfetch to sc_sys (int ack)
@
text
@d153 4
d215 2
d257 4
d282 1
a282 1
end rtl;
@


1.14
log
@VHDL restructure: add jopcpu + records for SimpCon
@
text
@d131 2
a132 1
	signal irq_in			: irq_in_type;
d195 1
a195 1
			irq_in, exc_req);
d200 1
a200 1
			irq_in, exc_req,
@


1.13
log
@VHDL restructure: add jopcpu + records for SimpCon
@
text
@d95 1
a95 7
	io_t	: inout std_logic_vector(6 downto 1);
--
--	dummy input pins for EP1C6 on board with EP1C12 pinout
--	EP1C12 has additional GND and VCCINT pins.
--
	dummy_gnd		: out std_logic_vector(5 downto 0);
	dummy_vccint	: out std_logic_vector(5 downto 0)
@


1.12
log
@Generate hardware exception (on stack overflow)
@
text
@d2 1
a2 1
--	jopsc.vhd
d4 1
a4 1
--	top level for cycore borad
d20 1
d30 1
a36 2
	exta_width	: integer := 3;		-- length of exta part in JOP microcode
	io_addr_bits	: integer := 7;	-- address bits of internal io
d95 7
a101 1
	io_t	: inout std_logic_vector(6 downto 1)
d119 4
a122 4
component core is
generic(jpc_width	: integer);			-- address bits of java bytecode pc
port (
	clk, reset	: in std_logic;
d124 2
a125 1
-- memio connection
d127 2
a128 22
	bsy			: in std_logic;
	din			: in std_logic_vector(31 downto 0);
	ext_addr	: out std_logic_vector(exta_width-1 downto 0);
	rd, wr		: out std_logic;

-- jbc connections

	jbc_addr	: out std_logic_vector(jpc_width-1 downto 0);
	jbc_data	: in std_logic_vector(7 downto 0);

-- interrupt from io

	irq			: in std_logic;
	irq_ena		: in std_logic;

	exc_int		: in std_logic;
	sp_ov		: out std_logic;

	aout		: out std_logic_vector(31 downto 0);
	bout		: out std_logic_vector(31 downto 0)
);
end component;
d130 9
d141 1
a141 1
--	Signals
d143 3
a145 1
	signal clk_int			: std_logic;
d147 1
a147 27
	signal stack_tos		: std_logic_vector(31 downto 0);
	signal stack_nos		: std_logic_vector(31 downto 0);
	signal rd, wr			: std_logic;
	signal ext_addr			: std_logic_vector(exta_width-1 downto 0);
	signal stack_din		: std_logic_vector(31 downto 0);

-- extension/mem interface

	signal mem_rd			: std_logic;
	signal mem_wr			: std_logic;
	signal mem_addr_wr		: std_logic;
	signal mem_bc_rd		: std_logic;
	signal mem_dout			: std_logic_vector(31 downto 0);
	signal mem_bcstart		: std_logic_vector(31 downto 0);
	signal mem_bsy			: std_logic;
	signal bsy				: std_logic;

	signal jbc_addr			: std_logic_vector(jpc_width-1 downto 0);
	signal jbc_data			: std_logic_vector(7 downto 0);

-- mem/sc interface

	signal sc_address		: std_logic_vector(20 downto 0);
	signal sc_wr_data		: std_logic_vector(31 downto 0);
	signal sc_rd, sc_wr		: std_logic;
	signal sc_rd_data		: std_logic_vector(31 downto 0);
	signal sc_rdy_cnt		: unsigned(1 downto 0);
a158 26
-- SimpCon io interface

	signal scio_address		: std_logic_vector(io_addr_bits-1 downto 0);
	signal scio_wr_data		: std_logic_vector(31 downto 0);
	signal scio_rd			: std_logic;
	signal scio_wr			: std_logic;
	signal scio_rd_data		: std_logic_vector(31 downto 0);
	signal scio_rdy_cnt		: unsigned(1 downto 0);

-- interrupt io interface

	signal io_irq			: std_logic;
	signal io_irq_ena		: std_logic;

	signal exc_req			: exception_type;
	signal exc_int			: std_logic;

	signal int_res			: std_logic;
	signal res_cnt			: unsigned(2 downto 0) := "000";	-- for the simulation

	signal wd_out, sp_ov	: std_logic;

	-- for generation of internal reset
	attribute altera_attribute : string;
	attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";

a189 3
	-- sp_ov indicates stack overflow
	-- We can use the wd LED
	-- wd <= sp_ov;
d192 4
a195 17
	cmp_core: core generic map(jpc_width)
		port map (clk_int, int_res,
			bsy,
			stack_din, ext_addr,
			rd, wr,
			jbc_addr, jbc_data,
			io_irq, io_irq_ena,
			exc_int, sp_ov,
			stack_tos, stack_nos
		);

	exc_req.spov <= sp_ov;

	cmp_ext: entity work.extension 
		generic map (
			exta_width => exta_width,
			io_addr_bits => io_addr_bits
d197 4
a200 27
		port map (
			clk => clk_int,
			reset => int_res,
			ain => stack_tos,
			bin => stack_nos,

			ext_addr => ext_addr,
			rd => rd,
			wr => wr,
			bsy => bsy,
			dout => stack_din,

			mem_rd => mem_rd,
			mem_wr => mem_wr,
			mem_addr_wr => mem_addr_wr,
			mem_bc_rd => mem_bc_rd,
			mem_data => mem_dout,
			mem_bcstart => mem_bcstart,
			mem_bsy => mem_bsy,
	
			scio_address => scio_address,
			scio_wr_data => scio_wr_data,
			scio_rd => scio_rd,
			scio_wr => scio_wr,
			scio_rd_data => scio_rd_data,
			scio_rdy_cnt => scio_rdy_cnt
		);
d203 4
a206 19
		generic map (
			addr_bits => io_addr_bits
		)
		port map (
			clk => clk_int,
			reset => int_res,

			address => scio_address,
			wr_data => scio_wr_data,
			rd => scio_rd,
			wr => scio_wr,
			rd_data => scio_rd_data,
			rdy_cnt => scio_rdy_cnt,

			irq => io_irq,
			irq_ena => io_irq_ena,
			exc_req => exc_req,
			exc_int => exc_int,
			
a217 30
	cmp_mem: entity work.mem_sc
		generic map (
			jpc_width => jpc_width,
			block_bits => block_bits,
			addr_bits => 21
		)
		port map (
			clk => clk_int,
			reset => int_res,
			din => stack_tos,

			mem_rd => mem_rd,
			mem_wr => mem_wr,
			mem_addr_wr => mem_addr_wr,
			mem_bc_rd => mem_bc_rd,
			dout => mem_dout,
			bcstart => mem_bcstart,
			bsy => mem_bsy,

			jbc_addr => jbc_addr,
			jbc_data => jbc_data,

			address => sc_address,
			wr_data => sc_wr_data,
			rd => sc_rd,
			wr => sc_wr,
			rd_data => sc_rd_data,
			rdy_cnt => sc_rdy_cnt
		);

d221 1
a221 2
			rom_ws => rom_cnt-1,
			addr_bits => 21
d223 2
a224 10
		port map (
			clk => clk_int,
			reset => int_res,

			address => sc_address,
			wr_data => sc_wr_data,
			rd => sc_rd,
			wr => sc_wr,
			rd_data => sc_rd_data,
			rdy_cnt => sc_rdy_cnt,
@


1.11
log
@splite jop_types to 'real' types and PLL setting
@
text
@d135 1
d201 3
d256 1
a256 1
			sp_ov,
d260 2
d312 3
@


1.10
log
@removed wb_pack
@
text
@d29 1
@


1.9
log
@changed addr_bits and rom_cnt to Simpcon memory interface
with Flash
@
text
@a28 1
use work.wb_pack.all;
@


1.8
log
@Memory mapped SimpCon IO devices are now standard
@
text
@d170 1
a170 1
	signal sc_address		: std_logic_vector(17 downto 0);
d321 1
a321 1
			addr_bits => 18
d350 2
a351 2
			rom_cnt => rom_cnt,
			addr_bits => 18
a412 1

@


1.7
log
@added io-pins for wishbone interface to extension
@
text
@d2 1
a2 1
--	jopcyc12.vhd
d4 1
a4 7
--	top level for new borad with EP1C12
--		use iocore.vhd for all io-pins
--
--	2002-06-27:	2088 LCs, 23.6 MHz
--	2002-07-27:	2308 LCs, 23.1 MHz	with some changes in jvm and baseio
--	2002-08-02:	2463 LCs
--	2002-08-08:	2431 LCs simpler sigdel
d17 1
a17 1
--	2005-06-09	added the bsy routing through extension
d19 1
d29 2
d35 5
a39 3
	exta_width	: integer := 3;		-- address bits of internal io
	ram_cnt		: integer := 3;		-- clock cycles for external ram
	rom_cnt		: integer := 15;		-- 3 clock cycles for external rom OK for 20 MHz
d41 1
a41 1
	block_bits	: integer := 3		-- 2*block_bits is number of cache blocks
a141 135
component extension is
generic (exta_width : integer);
port (
	clk, reset	: in std_logic;

-- core interface

	ain			: in std_logic_vector(31 downto 0);		-- from stack
	bin			: in std_logic_vector(31 downto 0);		-- from stack
	ext_addr	: in std_logic_vector(exta_width-1 downto 0);
	rd, wr		: in std_logic;
	bsy			: out std_logic;
	dout		: out std_logic_vector(31 downto 0);	-- to stack

-- mem interface

	mem_rd		: out std_logic;
	mem_wr		: out std_logic;
	mem_addr_wr	: out std_logic;
	mem_bc_rd	: out std_logic;
	mem_data	: in std_logic_vector(31 downto 0); 	-- output of memory module
	mem_bcstart	: in std_logic_vector(31 downto 0); 	-- start of method in bc cache
	mem_bsy		: in std_logic;
	
-- io interface

	io_rd		: out std_logic;
	io_wr		: out std_logic;
	io_addr_wr	: out std_logic;
	io_data		: in std_logic_vector(31 downto 0);		-- output of io module

-- io ports that go to the wishbone interface

	wb_io	: inout io_ports

);
end component;

component mem32 is
generic (jpc_width : integer; block_bits : integer; ram_cnt : integer; rom_cnt : integer);
port (

-- jop interface

	clk, reset	: in std_logic;

	din			: in std_logic_vector(31 downto 0);

	mem_rd		: in std_logic;
	mem_wr		: in std_logic;
	mem_addr_wr	: in std_logic;
	mem_bc_rd	: in std_logic;
	dout		: out std_logic_vector(31 downto 0);
	bcstart		: out std_logic_vector(31 downto 0); 	-- start of method in bc cache

	bsy			: out std_logic;

-- jbc connections

	jbc_addr	: in std_logic_vector(jpc_width-1 downto 0);
	jbc_data	: out std_logic_vector(7 downto 0);

--
--	two ram banks
--
	rama_a		: out std_logic_vector(17 downto 0);
	rama_d		: inout std_logic_vector(15 downto 0);
	rama_ncs	: out std_logic;
	rama_noe	: out std_logic;
	rama_nlb	: out std_logic;
	rama_nub	: out std_logic;
	rama_nwe	: out std_logic;
	ramb_a		: out std_logic_vector(17 downto 0);
	ramb_d		: inout std_logic_vector(15 downto 0);
	ramb_ncs	: out std_logic;
	ramb_noe	: out std_logic;
	ramb_nlb	: out std_logic;
	ramb_nub	: out std_logic;
	ramb_nwe	: out std_logic;

--
--	config/program flash and big nand flash
--
	fl_a	: out std_logic_vector(18 downto 0);
	fl_d	: inout std_logic_vector(7 downto 0);
	fl_ncs	: out std_logic;
	fl_ncsb	: out std_logic;
	fl_noe	: out std_logic;
	fl_nwe	: out std_logic;
	fl_rdy	: in std_logic

);
end component;

component io is
generic (clk_freq : integer);
port (

-- jop interface

	clk, reset	: in std_logic;

	din			: in std_logic_vector(31 downto 0);

-- interface to mem

	rd, wr		: in std_logic;
	addr_wr		: in std_logic;

	dout		: out std_logic_vector(31 downto 0);

-- interrupt

	irq			: out std_logic;
	irq_ena		: out std_logic;

-- serial interface

	txd			: out std_logic;
	rxd			: in std_logic;
	ncts		: in std_logic;
	nrts		: out std_logic;

-- watch dog

	wd			: out std_logic;

--	I/O pins of board

	b		: inout std_logic_vector(10 downto 1);
	l		: inout std_logic_vector(20 downto 1);
	r		: inout std_logic_vector(20 downto 1);
	t		: inout std_logic_vector(6 downto 1)
);
end component;
d154 2
d168 29
a196 4
	signal io_rd			: std_logic;
	signal io_wr			: std_logic;
	signal io_addr_wr		: std_logic;
	signal io_dout			: std_logic_vector(31 downto 0);
d205 1
a205 1
	-- for generationg internal reset
d240 3
d256 31
a286 10
	cmp_ext: extension generic map (exta_width)
		port map (clk_int, int_res, stack_tos, stack_nos,
			ext_addr, rd, wr, bsy, stack_din,
			mem_rd, mem_wr, mem_addr_wr, mem_bc_rd,
			mem_dout, mem_bcstart, mem_bsy,
			io_rd, io_wr, io_addr_wr, io_dout,
			wb_io.b => io_b,
			wb_io.l => io_l,
			wb_io.r => io_r,
			wb_io.t => io_t
d289 27
d317 28
a344 9
	cmp_mem: mem32 generic map (jpc_width, block_bits, ram_cnt, rom_cnt)
		port map (clk_int, int_res, stack_tos,
			mem_rd, mem_wr, mem_addr_wr, mem_bc_rd,
			mem_dout, mem_bcstart,
			mem_bsy,
			jbc_addr, jbc_data,
			rama_a, rama_d, rama_ncs, rama_noe, rama_nlb, rama_nub, rama_nwe,
			ramb_a, ramb_d, ramb_ncs, ramb_noe, ramb_nlb, ramb_nub, ramb_nwe,
			fl_a, fl_d, fl_ncs, fl_ncsb, fl_noe, fl_nwe, fl_rdy
d347 33
a379 7
	cmp_io: io generic map (clk_freq)
		port map (clk_int, int_res, stack_tos,
			io_rd, io_wr, io_addr_wr, io_dout,
			io_irq, io_irq_ena,
			ser_txd, ser_rxd, ser_ncts, ser_nrts,
			wd_out,
			io_b, io_l, io_r, io_t
d382 32
@


1.6
log
@sp_ov for stack overflow detecion with a LED (e.g. wd LED)
@
text
@d172 6
a177 1
	io_data		: in std_logic_vector(31 downto 0)		-- output of io module
d367 5
a371 1
			io_rd, io_wr, io_addr_wr, io_dout
d374 1
@


1.5
log
@added the (missing) bsy routing through extension
@
text
@d24 1
d136 2
d307 2
d344 2
d353 1
d381 1
a381 1
			wd,
@


1.4
log
@resync with current development
@
text
@d23 1
d151 1
d162 1
d289 1
d341 1
a341 1
			mem_bsy,
d351 1
a351 1
			ext_addr, rd, wr, stack_din,
d353 1
a353 1
			mem_dout, mem_bcstart,
@


1.3
log
@Thesis version
@
text
@d31 2
a35 1
	clk_freq	: integer := 20000000;	-- 20 MHz clock frequency
d38 3
a40 2
	rom_cnt		: integer := 3;		-- clock cycles for external rom OK for 20 MHz
	jpc_width	: integer := 10	-- address bits of java byte code pc
d105 1
d113 1
d171 1
a171 1
generic (jpc_width : integer; ram_cnt : integer; rom_cnt : integer);
d298 5
a302 1
	signal res_cnt			: unsigned(2 downto 0);
d325 9
a333 5
--	pll_inst : pll port map (
--		inclk0	 => clk,
--		c0	 => clk_int
--	);
	clk_int <= clk;
d335 1
a335 1
	cmp_core: core 
d353 1
a353 1
	cmp_mem: mem32 generic map (jpc_width, ram_cnt, rom_cnt)
@


1.2
log
@new module structure (extentions.vhd).
@
text
@d4 1
a4 1
--	top level for new borad
d22 1
d34 1
a34 2
--	clk_freq	: integer := 20000000;	-- 20 MHz clock frequency
clk_freq	: integer := 100000000;	-- 100 MHz clock frequency
d37 1
a37 2
--	rom_cnt		: integer := 3;		-- clock cycles for external rom OK for 20 MHz
rom_cnt		: integer := 15;		-- clock cycles for external rom for 100 MHz
d44 1
a44 1
---- serial interface
a123 2
	jpc_wr		: out std_logic;
	bc_wr		: out std_logic;
d130 2
a131 1
	dout		: out std_logic_vector(31 downto 0)
d142 2
a143 1
	din			: in std_logic_vector(31 downto 0);		-- from stack
d153 1
d155 1
d179 1
d181 1
a188 2
	jpc_wr		: in std_logic;
	bc_wr		: in std_logic;
d270 1
d278 1
d280 1
a284 2
	signal jpc_wr			: std_logic;
	signal bc_wr			: std_logic;
d317 5
a321 5
	pll_inst : pll port map (
		inclk0	 => clk,
		c0	 => clk_int
	);
--	clk_int <= clk;
d328 1
a328 1
			jbc_addr, jbc_data, jpc_wr, bc_wr,
d330 1
a330 1
			stack_tos
d334 1
a334 1
		port map (clk_int, int_res, stack_tos,
d336 2
a337 1
			mem_rd, mem_wr, mem_addr_wr, mem_dout,
d343 2
a344 1
			mem_rd, mem_wr, mem_addr_wr, mem_dout,
d346 1
a346 1
			jbc_addr, jbc_data, jpc_wr, bc_wr,
@


1.1
log
@resync of actual development.
@
text
@d2 1
a2 1
--	jopcyc.vhd
d4 1
a4 1
--	top level for Cyclone board with EP1C12
d21 1
d33 3
a35 4
	clk_freq	: integer := 20000000;	-- 20 MHz clock frequency
-- clk_freq	: integer := 100000000;	-- 100 MHz clock frequency
	width		: integer := 32;	-- one data word
	ioa_width	: integer := 3;		-- address bits of internal io
d37 3
a39 2
	rom_cnt		: integer := 3		-- clock cycles for external rom
--	rom_cnt		: integer := 30		-- clock cycles for external rom
d117 2
a118 2
	din			: in std_logic_vector(width-1 downto 0);
	addr		: out std_logic_vector(ioa_width-1 downto 0);
d121 7
d133 29
a161 1
	dout		: out std_logic_vector(width-1 downto 0)
d166 1
a166 1
generic (width : integer; ioa_width : integer; ram_cnt : integer; rom_cnt : integer);
d173 6
a178 3
	din			: in std_logic_vector(width-1 downto 0);
	addr		: in std_logic_vector(ioa_width-1 downto 0);
	rd, wr		: in std_logic;
d181 7
a187 1
	dout		: out std_logic_vector(width-1 downto 0);
d216 1
a216 8
	fl_rdy	: in std_logic;

-- io interface

	io_din		: in std_logic_vector(width-1 downto 0);
	io_rd		: out std_logic;
	io_wr		: out std_logic;
	io_addr_wr	: out std_logic
d229 1
a229 1
	din			: in std_logic_vector(width-1 downto 0);
d236 1
a236 1
	dout		: out std_logic_vector(width-1 downto 0);
d268 4
a271 1
	signal memio_din		: std_logic_vector(width-1 downto 0);
a272 1
	signal mem_addr			: std_logic_vector(ioa_width-1 downto 0);
d275 2
d278 5
a282 1
	signal mem_dout			: std_logic_vector(width-1 downto 0);
d287 1
a287 1
	signal io_dout			: std_logic_vector(width-1 downto 0);
d315 5
a319 5
--	pll_inst : pll port map (
--		inclk0	 => clk,
--		c0	 => clk_int
--	);
	clk_int <= clk;
d324 3
a326 2
			mem_dout, mem_addr,
			mem_rd, mem_wr,
d328 1
a328 1
			memio_din
d331 6
d338 5
a342 2
	cmp_mem: mem32 generic map (width, ioa_width, ram_cnt, rom_cnt)
		port map (clk_int, int_res, memio_din, mem_addr, mem_rd, mem_wr, mem_bsy, mem_dout,
d345 1
a345 2
			fl_a, fl_d, fl_ncs, fl_ncsb, fl_noe, fl_nwe, fl_rdy,
			io_dout, io_rd, io_wr, io_addr_wr
d349 1
a349 1
		port map (clk_int, int_res, memio_din,
a356 3
--
--	EP1C12 additional power pins as tristatet output on EP1C6
--
@