head	1.5;
access;
symbols
	bg2_23:1.5
	bg2_22:1.5
	bg2_21:1.5
	bg2_20:1.5
	bg2_16:1.5
	bg2_15:1.5
	bg2_12:1.5
	bg2_07:1.5
	isorc2008_submission:1.4
	handbook_alpha_edition:1.4
	jtres2007_submission:1.4
	bg1_07:1.4
	bg1_06:1.4
	bg1_05:1.4
	TAL_101:1.4
	TAL_100:1.4
	jtres_submission:1.3
	wises06_submission:1.3
	lctes2006_submission:1.3
	rtgc_isorc2006:1.3.0.4
	isorc2006:1.3.0.2
	rtgc_paper:1.3
	bg1_00:1.2
	nohandle:1.1;
locks; strict;
comment	@# @;


1.5
date	2008.02.23.23.18.44;	author martin;	state Exp;
branches;
next	1.4;
commitid	b7347c0a9b84567;

1.4
date	2006.08.07.19.35.32;	author martin;	state Exp;
branches;
next	1.3;
commitid	6a7844d796024567;

1.3
date	2005.11.13.20.50.33;	author martin;	state Exp;
branches;
next	1.2;
commitid	55134377a7174567;

1.2
date	2005.08.16.12.39.55;	author martin;	state Exp;
branches;
next	1.1;
commitid	1c5c4301de864567;

1.1
date	2005.05.11.16.55.14;	author martin;	state Exp;
branches;
next	;
commitid	244c428238f04567;


desc
@@


1.5
log
@JOP goes GPL
@
text
@--
--
--  This file is a part of JOP, the Java Optimized Processor
--
--  Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--


------------------------------------------------------------------
--
-- A very simple memory model
-- use variables instead of signals to save time and memory
--
------------------------------------------------------------------
------------------------------------------------------------------
library std;
use std.textio.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- use IEEE.std_logic_textio.all;          -- I/O for logic types

entity memory is
	generic(add_bits : integer := 18;
		data_bits : integer := 32);
	port(
		addr	: in std_logic_vector(add_bits-1 downto 0);
		data	: inout std_logic_vector(data_bits-1 downto 0);
		ncs		: in std_logic;
		noe		: in std_logic;
		nwr		: in std_logic);
 
	subtype word is std_logic_vector(data_bits-1 downto 0);
	constant nwords : integer := 2 ** add_bits;
	type ram_type is array(0 to nwords-1) of word;
end;


architecture sim of memory is
	------------------------------
	shared variable ram : ram_type;
	------------------------------
	constant tAcc : time := 17 ns;	-- original 15ns
--	constant tAcc : time := 27 ns;
	constant tDoe : time := 9 ns;	-- original 7ns
--	constant tDoe : time := 19 ns;	-- original 7ns
	constant tHold : time := 2 ns;

	signal cs_ok	: std_logic;
	signal oe_ok	: std_logic;

begin

memory:
process (addr, data, ncs, cs_ok, noe, oe_ok, nwr)
	variable address : natural;

begin
		address := to_integer(unsigned(addr));
		if ncs='0' then
			cs_ok <= '1' after tAcc;
		else
			cs_ok <= '0';
		end if;
		if noe='0' then
			oe_ok <= '1' after tDoe;
		else
			oe_ok <= '0';
		end if;
		if cs_ok='1' and oe_ok='1' then
			data <= ram(address);
		else
			data <= (others => 'Z') after tHold;
		end if;
		if ncs='0' and rising_edge(nwr) then
			ram(address) := data;
		end if;
end process;


-- initialize at start with a second process accessing
-- the shared variable ram

initialize:
process

	variable address	: natural;
	variable cnt		: natural;

	file memfile		: text is "mem_main.dat";
	variable memline	: line; 
	variable l 			: line;
	variable val		: integer;
	variable data32		: std_logic_vector(31 downto 0);

variable x : integer;

	begin
		write(output, "load main memory...");
		for address in 0 to nwords-1 loop
			if endfile(memfile) then
				exit;
			end if;
			readline(memfile, memline);
			read(memline, val);
			if data_bits=32 then
				ram(address) := std_logic_vector(to_signed(val, data_bits));
			else
				-- simulate a 16 bit SRAM
				data32 := std_logic_vector(to_signed(val, 32));
				ram(address*2) := data32(31 downto 16);
				ram(address*2+1) := data32(15 downto 0);
			end if;

			cnt := address;
		end loop;
		file_close(memfile);
		cnt := cnt+1;
		write(output, " words: ");
		write(l, cnt);
		writeline(output, l);
		-- we're done, wait forever
		wait;
	end process initialize;

end architecture sim;

@


1.4
log
@version for 32 and 16 bit memory
@
text
@d1 21
@


1.3
log
@Better simulation of noe and ncs timing.
@
text
@d88 2
d100 9
a108 1
			ram(address) := std_logic_vector(to_signed(val, data_bits));
@


1.2
log
@Change to new .jop format: use first word as length for the Java application.
@
text
@d37 4
a40 1
	constant tAcc : time := 17 ns;
d43 3
d49 1
a49 1
process (addr, data, ncs, noe, nwr)
d54 12
a65 2
		if noe='0' and ncs='0' then
			data <= ram(address) after tAcc;
@


1.1
log
@resync with current development
@
text
@d18 1
a18 1
	generic(add_bits : integer := 12;
d66 1
d70 1
d75 1
a75 1
--		write(output, "load main memory...");
d83 1
d86 4
@