head 1.14; access; symbols bg2_23:1.14 bg2_22:1.14 bg2_21:1.14 bg2_20:1.14 bg2_16:1.14 bg2_15:1.13 bg2_12:1.13 bg2_07:1.13 isorc2008_submission:1.10 handbook_alpha_edition:1.9 jtres2007_submission:1.9 bg1_07:1.4 bg1_06:1.4 bg1_05:1.4 TAL_101:1.4 TAL_100:1.4 jtres_submission:1.4 wises06_submission:1.4 lctes2006_submission:1.4; locks; strict; comment @# @; 1.14 date 2008.06.20.15.43.05; author martin; state Exp; branches; next 1.13; commitid 6ab6485bd0044567; 1.13 date 2008.02.23.23.18.46; author martin; state Exp; branches; next 1.12; commitid b7347c0a9b84567; 1.12 date 2008.02.21.16.37.42; author 9914pich; state Exp; branches; next 1.11; commitid 395447bda8d54567; 1.11 date 2008.02.20.14.29.30; author martin; state Exp; branches; next 1.10; commitid 4d7c47bc39384567; 1.10 date 2007.12.02.15.36.09; author martin; state Exp; branches; next 1.9; commitid 177b4752d0e24567; 1.9 date 2007.06.05.16.33.29; author martin; state Exp; branches; next 1.8; commitid 5e78466590554567; 1.8 date 2007.06.05.13.03.55; author martin; state Exp; branches; next 1.7; commitid 49046655f384567; 1.7 date 2007.06.04.19.37.53; author martin; state Exp; branches; next 1.6; commitid 2b6646646a104567; 1.6 date 2007.06.01.17.13.27; author 9914pich; state Exp; branches; next 1.5; commitid 5e95466053b54567; 1.5 date 2007.05.21.19.55.15; author martin; state Exp; branches; next 1.4; commitid 2334651f9224567; 1.4 date 2006.01.12.11.03.30; author martin; state Exp; branches; next 1.3; commitid 182e43c637534567; 1.3 date 2006.01.11.14.13.02; author martin; state Exp; branches; next 1.2; commitid 293a43c5120d4567; 1.2 date 2005.12.28.17.22.47; author martin; state Exp; branches; next 1.1; commitid ed743b2c9e54567; 1.1 date 2005.12.23.01.05.16; author martin; state Exp; branches; next ; commitid 31dd43ab4d4b4567; desc @@ 1.14 log @CPU count from sys device @ text @-- -- -- This file is a part of JOP, the Java Optimized Processor -- -- Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . -- -- -- scio_lego.vhd -- -- io devices for LEGO MindStorms -- -- -- io address mapping: -- -- IO Base is 0xffffff80 for 'fast' constants (bipush) -- -- 0x00 0-3 system clock counter, us counter, timer int, wd bit -- 0x10 0-1 uart (download) -- 0x30 LEGO interface -- -- status word in uarts: -- 0 uart transmit data register empty -- 1 uart read data register full -- -- -- todo: -- -- -- 2003-07-09 created -- 2005-08-27 ignore ncts on uart -- 2005-11-30 changed to SimpCon -- 2007-03-26 changed for Lego PCB -- 2007-05-15 adapted to SimpCon changes -- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.jop_types.all; use work.sc_pack.all; use work.jop_config.all; entity scio is generic (cpu_id : integer := 0; cpu_cnt : integer := 1); port ( clk : in std_logic; reset : in std_logic; -- -- SimpCon IO interface -- sc_io_out : in sc_out_type; sc_io_in : out sc_in_type; -- -- Interrupts from IO devices -- irq_in : out irq_bcf_type; irq_out : in irq_ack_type; exc_req : in exception_type; -- CMP sync_out : in sync_out_type := NO_SYNC; sync_in : out sync_in_type; -- serial interface -- slightly abused in this design txd : out std_logic; rxd : in std_logic; -- not connected in this design ncts : in std_logic; -- ss3 in this design nrts : out std_logic; -- watch dog wd : out std_logic; -- core i/o pins l : inout std_logic_vector(20 downto 1); r : inout std_logic_vector(20 downto 1); t : inout std_logic_vector(6 downto 1); b : inout std_logic_vector(10 downto 1) ); end scio; architecture rtl of scio is constant SLAVE_CNT : integer := 4; -- SLAVE_CNT <= 2**DECODE_BITS constant DECODE_BITS : integer := 2; -- number of bits that can be used inside the slave constant SLAVE_ADDR_BITS : integer := 4; type slave_bit is array(0 to SLAVE_CNT-1) of std_logic; signal sc_rd, sc_wr : slave_bit; type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0); signal sc_dout : slave_dout; type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0); signal sc_rdy_cnt : slave_rdy_cnt; signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1; signal nrts_ignored : std_logic; begin -- -- unused and input pins tri state -- t(5) <= 'Z'; -- ss0 t(6) <= 'Z'; -- ss1 t(3) <= 'Z'; -- sclk nrts <= 'Z'; -- ss2 l(3) <= 'Z'; -- sdi b(9) <= 'Z'; -- s2pi b(8) <= 'Z'; -- s1pi b(7) <= 'Z'; -- s0pi b(5) <= 'Z'; -- s2di b(2) <= 'Z'; -- s1di b(1) <= 'Z'; -- s0di l(2) <= 'Z'; -- sdo r(19 downto 14) <= (others => 'Z'); -- sd-card assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio"; sel <= to_integer(unsigned(sc_io_out.address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS))); -- What happens when sel_reg > SLAVE_CNT-1?? sc_io_in.rd_data <= sc_dout(sel_reg); sc_io_in.rdy_cnt <= sc_rdy_cnt(sel_reg); -- -- Connect SLAVE_CNT slaves -- gsl: for i in 0 to SLAVE_CNT-1 generate sc_rd(i) <= sc_io_out.rd when i=sel else '0'; sc_wr(i) <= sc_io_out.wr when i=sel else '0'; end generate; -- -- Register read and write mux selector -- process(clk, reset) begin if (reset='1') then sel_reg <= 0; elsif rising_edge(clk) then if sc_io_out.rd='1' or sc_io_out.wr='1' then sel_reg <= sel; end if; end if; end process; cmp_sys: entity work.sc_sys generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq, cpu_id => cpu_id, cpu_cnt => cpu_cnt ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(0), wr => sc_wr(0), rd_data => sc_dout(0), rdy_cnt => sc_rdy_cnt(0), irq_in => irq_in, irq_out => irq_out, exc_req => exc_req, sync_out => sync_out, sync_in => sync_in, wd => wd ); cmp_ua: entity work.sc_uart generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq, baud_rate => 115200, txf_depth => 2, txf_thres => 1, rxf_depth => 2, rxf_thres => 1 ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), txd => txd, rxd => rxd, ncts => '0', nrts => nrts_ignored ); -- slave 2 is reserved for USB and System.out writes to it!!! cmp_usb: entity work.sc_usb generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(2), wr => sc_wr(2), rd_data => sc_dout(2), rdy_cnt => sc_rdy_cnt(2), data => r(8 downto 1), nrxf => r(9), ntxe => r(10), nrd => r(11), ft_wr => r(12), nsi => r(13) ); cmp_lego: entity work.sc_lego generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(3), wr => sc_wr(3), rd_data => sc_dout(3), rdy_cnt => sc_rdy_cnt(3), -- LEGO interface -- speaker speaker => l(1), -- motor stuff m0en => l(4), m0dir => l(5), m0break => l(6), m0dia => l(13), m0doa => l(14), m0dib => l(15), m0dob => l(16), m1en => l(8), m1dir => l(9), m1break => l(7), m1dia => l(17), m1doa => l(18), m1dib => l(19), m1dob => l(20), m2en => l(10), m2dir => l(11), m2break => l(12), -- sensor stuff s0di => b(1), s0do => b(3), s0pi => b(7), s1di => b(2), s1do => b(4), s1pi => b(8), s2di => b(5), s2do => b(6), s2pi => b(9), -- microphone mic1do => b(10), mic1 => r(20), -- pld pld_strobe => t(1), pld_data => t(2), pld_clk => t(4) ); end rtl; @ 1.13 log @JOP goes GPL @ text @d62 1 a62 1 generic (cpu_id : integer := 0); d194 2 a195 1 cpu_id => cpu_id @ 1.12 log @Mux selector register also changes at write @ text @d2 21 @ 1.11 log @Cleanup of SimpCon types @ text @d156 13 a168 13 -- -- Register read mux selector -- process(clk, reset) begin if (reset='1') then sel_reg <= 0; elsif rising_edge(clk) then if sc_io_out.rd='1' then sel_reg <= sel; end if; end if; end process; @ 1.10 log @additional signal from bcfetch to sc_sys (int ack) @ text @d50 1 a50 1 sc_io_out : in sc_io_out_type; @ 1.9 log @no message @ text @d56 2 a57 1 irq_in : out irq_in_type; d187 1 @ 1.8 log @use rdy_cnt in scio devices, return "00" for USB device at address 2 @ text @a143 3 -- default for unused USB device sc_dout(2) <= (others => '0'); sc_rdy_cnt(2) <= (others => '0'); @ 1.7 log @add cpu_id as generic @ text @d143 4 a146 2 -- sc_io_in.rdy_cnt <= sc_rdy_cnt(sel_reg); sc_io_in.rdy_cnt <= "00"; @ 1.6 log @no message @ text @d41 2 d171 3 a173 3 addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq, cpu_id => 0 @ 1.5 log @LEGO roboter first release @ text @d57 4 d168 1 a168 1 cmp_cnt: entity work.sc_cnt generic map ( d170 2 a171 1 clk_freq => clk_freq d187 3 @ 1.4 log @Generate hardware exception (on stack overflow) @ text @d26 2 a27 1 -- d36 1 a39 1 generic (addr_bits : integer); d41 3 a43 3 port ( clk : in std_logic; reset : in std_logic; d45 5 a49 1 -- SimpCon interface d51 6 a56 5 address : in std_logic_vector(addr_bits-1 downto 0); wr_data : in std_logic_vector(31 downto 0); rd, wr : in std_logic; rd_data : out std_logic_vector(31 downto 0); rdy_cnt : out unsigned(1 downto 0); d58 2 a59 1 -- interrupt d61 2 a62 2 irq : out std_logic; irq_ena : out std_logic; d64 2 a65 1 -- exception d67 2 a68 9 exc_req : in exception_type; exc_int : out std_logic; -- serial interface txd : out std_logic; rxd : in std_logic; ncts : in std_logic; nrts : out std_logic; d72 1 a72 1 wd : out std_logic; d75 5 a79 5 l : inout std_logic_vector(20 downto 1); r : inout std_logic_vector(20 downto 1); t : inout std_logic_vector(6 downto 1); b : inout std_logic_vector(10 downto 1) ); d85 8 a92 8 constant SLAVE_CNT : integer := 4; -- SLAVE_CNT <= 2**DECODE_BITS constant DECODE_BITS : integer := 2; -- number of bits that can be used inside the slave constant SLAVE_ADDR_BITS : integer := 4; type slave_bit is array(0 to SLAVE_CNT-1) of std_logic; signal sc_rd, sc_wr : slave_bit; d94 2 a95 2 type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0); signal sc_dout : slave_dout; d97 2 a98 2 type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0); signal sc_rdy_cnt : slave_rdy_cnt; d100 3 a102 1 signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1; a108 7 t(5 downto 4) <= (others => 'Z'); l(17 downto 16) <= (others => 'Z'); l(11 downto 9) <= (others => 'Z'); l(7 downto 1) <= (others => 'Z'); r(20 downto 13) <= (others => 'Z'); r(11 downto 1) <= (others => 'Z'); b <= (others => 'Z'); d110 16 a125 1 assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio"; d127 7 a133 1 sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS))); d136 3 a138 2 rd_data <= sc_dout(sel_reg); rdy_cnt <= sc_rdy_cnt(sel_reg); d141 1 a141 1 -- Connect SLAVE_CNT simple test slaves d145 2 a146 2 sc_rd(i) <= rd when i=sel else '0'; sc_wr(i) <= wr when i=sel else '0'; d150 21 a170 21 -- -- Register read mux selector -- process(clk, reset) begin if (reset='1') then sel_reg <= 0; elsif rising_edge(clk) then if rd='1' then sel_reg <= sel; end if; end if; end process; cmp_cnt: entity work.sc_cnt generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq ) port map( clk => clk, reset => reset, d172 2 a173 2 address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, d179 1 a179 3 irq => irq, irq_ena => irq_ena, a180 1 exc_int => exc_int, d183 73 a255 1 ); d257 45 a301 64 cmp_ua: entity work.sc_uart generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq, baud_rate => 115200, txf_depth => 2, txf_thres => 1, rxf_depth => 2, rxf_thres => 1 ) port map( clk => clk, reset => reset, address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), txd => txd, rxd => rxd, ncts => '0', nrts => nrts ); -- slave 2 is reserved for USB and System.out writes to it!!! cmp_lego: entity work.sc_lego generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq ) port map( clk => clk, reset => reset, address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, rd => sc_rd(3), wr => sc_wr(3), rd_data => sc_dout(3), rdy_cnt => sc_rdy_cnt(3), -- LEGO interface -- motor stuff -- schematics wire names: ma_en => l(14), -- en1 ma_l1 => l(15), -- in1a ma_l2 => l(20), -- in1b ma_l1_sdi => t(1), -- sdi3 ma_l1_sdo => r(12), -- sdo3 ma_l2_sdi => t(2), -- sdi2 ma_l2_sdo => l(8), -- sdo2 mb_en => l(19), -- en2 mb_l1 => l(13), -- in2a mb_l2 => l(18), -- in2b -- sensor stuff s1_pow => l(12), -- sp1 s1_sdi => t(3), -- sdi1 s1_sdo => t(6) -- sdo1 ); @ 1.3 log @splite jop_types to 'real' types and PLL setting @ text @d57 5 d163 4 @ 1.2 log @comment @ text @d35 1 @ 1.1 log @LEGO interface @ text @d13 1 a13 1 -- 0x20 LEGO interface @