head 1.12; access; symbols bg2_23:1.12 bg2_22:1.12 bg2_21:1.12 bg2_20:1.12 bg2_16:1.12 bg2_15:1.11 bg2_12:1.11 bg2_07:1.11 isorc2008_submission:1.6 handbook_alpha_edition:1.5 jtres2007_submission:1.5; locks; strict; comment @# @; 1.12 date 2008.06.20.15.43.05; author martin; state Exp; branches; next 1.11; commitid 6ab6485bd0044567; 1.11 date 2008.02.23.23.18.46; author martin; state Exp; branches; next 1.10; commitid b7347c0a9b84567; 1.10 date 2008.02.22.14.09.16; author 9914pich; state Exp; branches; next 1.9; commitid 241647bed78a4567; 1.9 date 2008.02.22.13.18.20; author 9914pich; state Exp; branches; next 1.8; commitid d9447becb9b4567; 1.8 date 2008.02.21.16.37.42; author 9914pich; state Exp; branches; next 1.7; commitid 395447bda8d54567; 1.7 date 2008.02.20.14.29.30; author martin; state Exp; branches; next 1.6; commitid 4d7c47bc39384567; 1.6 date 2007.12.02.15.36.09; author martin; state Exp; branches; next 1.5; commitid 177b4752d0e24567; 1.5 date 2007.06.05.13.03.55; author martin; state Exp; branches; next 1.4; commitid 49046655f384567; 1.4 date 2007.06.04.19.37.53; author martin; state Exp; branches; next 1.3; commitid 2b6646646a104567; 1.3 date 2007.06.01.15.35.23; author 9914pich; state Exp; branches; next 1.2; commitid 1a3646603cb84567; 1.2 date 2007.03.18.02.10.12; author martin; state Exp; branches; next 1.1; commitid 74c445fc9f824567; 1.1 date 2007.03.07.14.13.23; author martin; state Exp; branches; next ; commitid 5d9b45eec8814567; desc @@ 1.12 log @CPU count from sys device @ text @-- -- -- This file is a part of JOP, the Java Optimized Processor -- -- Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . -- -- -- scio_dspiomin.vhd -- -- minimal io devices for dspio board -- -- -- io address mapping: -- -- IO Base is 0xffffff80 for 'fast' constants (bipush) -- -- 0x00 0-3 system clock counter, us counter, timer int, wd bit -- 0x10 0-1 uart (download) -- 0x20 0-1 USB connection (download) -- -- status word in uarts: -- 0 uart transmit data register empty -- 1 uart read data register full -- -- -- todo: -- -- -- 2003-07-09 created -- 2005-08-27 ignore ncts on uart -- 2005-11-30 changed to SimpCon -- 2005-12-20 dspio board -- 2007-03-17 use records -- -- Library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.jop_types.all; use work.sc_pack.all; use work.jop_config.all; entity scio is generic (cpu_id : integer := 0; cpu_cnt : integer := 1); port ( clk : in std_logic; reset : in std_logic; -- -- SimpCon IO interface -- sc_io_out : in sc_out_type; sc_io_in : out sc_in_type; -- -- Interrupts from IO devices -- irq_in : out irq_bcf_type; irq_out : in irq_ack_type; exc_req : in exception_type; -- CMP sync_out : in sync_out_type := NO_SYNC; sync_in : out sync_in_type; -- serial interface txd : out std_logic; rxd : in std_logic; ncts : in std_logic; nrts : out std_logic; -- watch dog wd : out std_logic; -- core i/o pins l : inout std_logic_vector(20 downto 1); r : inout std_logic_vector(20 downto 1); t : inout std_logic_vector(6 downto 1); b : inout std_logic_vector(10 downto 1) -- remove the comment for RAM access counting -- ram_cnt : in std_logic ); end scio; architecture rtl of scio is constant SLAVE_CNT : integer := 3; -- SLAVE_CNT <= 2**DECODE_BITS -- take care of USB address 0x20! constant DECODE_BITS : integer := 2; -- number of bits that can be used inside the slave constant SLAVE_ADDR_BITS : integer := 4; type slave_bit is array(0 to SLAVE_CNT-1) of std_logic; signal sc_rd, sc_wr : slave_bit; type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0); signal sc_dout : slave_dout; type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0); signal sc_rdy_cnt : slave_rdy_cnt; signal sel, sel_reg : integer range 0 to 2**DECODE_BITS-1; -- remove the comment for RAM access counting -- signal ram_count : std_logic; begin -- -- unused and input pins tri state -- l <= (others => 'Z'); r(20 downto 14) <= (others => 'Z'); t <= (others => 'Z'); b <= (others => 'Z'); assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio"; sel <= to_integer(unsigned(sc_io_out.address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS))); -- What happens when sel_reg > SLAVE_CNT-1?? sc_io_in.rd_data <= sc_dout(sel_reg); sc_io_in.rdy_cnt <= sc_rdy_cnt(sel_reg); -- -- Connect SLAVE_CNT simple slaves -- gsl: for i in 0 to SLAVE_CNT-1 generate sc_rd(i) <= sc_io_out.rd when i=sel else '0'; sc_wr(i) <= sc_io_out.wr when i=sel else '0'; end generate; -- -- Register read and write mux selector -- process(clk, reset) begin if (reset='1') then sel_reg <= 0; elsif rising_edge(clk) then if sc_io_out.rd='1' or sc_io_out.wr='1' then sel_reg <= sel; end if; end if; end process; cmp_sys: entity work.sc_sys generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq, cpu_id => cpu_id, cpu_cnt => cpu_cnt ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(0), wr => sc_wr(0), rd_data => sc_dout(0), rdy_cnt => sc_rdy_cnt(0), irq_in => irq_in, irq_out => irq_out, exc_req => exc_req, sync_out => sync_out, sync_in => sync_in, wd => wd -- remove the comment for RAM access counting -- ram_count => ram_count ); -- remove the comment for RAM access counting -- ram_count <= ram_cnt; cmp_ua: entity work.sc_uart generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq, baud_rate => 115200, txf_depth => 2, txf_thres => 1, rxf_depth => 2, rxf_thres => 1 ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), rdy_cnt => sc_rdy_cnt(1), txd => txd, rxd => rxd, ncts => '0', nrts => nrts ); cmp_usb: entity work.sc_usb generic map ( addr_bits => SLAVE_ADDR_BITS, clk_freq => clk_freq ) port map( clk => clk, reset => reset, address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), wr_data => sc_io_out.wr_data, rd => sc_rd(2), wr => sc_wr(2), rd_data => sc_dout(2), rdy_cnt => sc_rdy_cnt(2), data => r(8 downto 1), nrxf => r(9), ntxe => r(10), nrd => r(11), ft_wr => r(12), nsi => r(13) ); end rtl; @ 1.11 log @JOP goes GPL @ text @d62 1 a62 1 generic (cpu_id : integer := 0); d176 2 a177 1 cpu_id => cpu_id @ 1.10 log @no message @ text @d2 21 @ 1.9 log @included atomic @ text @a164 1 atomic => sc_io_out.atomic, a199 1 atomic => sc_io_out.atomic, a220 1 atomic => sc_io_out.atomic, @ 1.8 log @Mux selector register also changes at write @ text @d80 3 d106 3 d165 1 d177 2 d180 3 d201 1 d223 1 @ 1.7 log @Cleanup of SimpCon types @ text @d133 1 a133 1 -- Register read mux selector d140 1 a140 1 if sc_io_out.rd='1' then @ 1.6 log @additional signal from bcfetch to sc_sys (int ack) @ text @d49 1 a49 1 sc_io_out : in sc_io_out_type; @ 1.5 log @use rdy_cnt in scio devices, return "00" for USB device at address 2 @ text @d55 2 a56 1 irq_in : out irq_in_type; d163 1 @ 1.4 log @add cpu_id as generic @ text @d85 1 a85 1 constant SLAVE_CNT : integer := 4; @ 1.3 log @no message @ text @d41 1 a41 1 d148 1 a148 1 cpu_id => 0 @ 1.2 log @VHDL restructure: add jopcpu + records for SimpCon @ text @d58 5 d145 1 a145 1 cmp_cnt: entity work.sc_cnt generic map ( d147 2 a148 1 clk_freq => clk_freq d164 3 @ 1.1 log @dspio board without AC97 interface @ text @d15 1 a15 1 -- status word in uart and usb: d27 1 d37 1 a40 1 generic (addr_bits : integer); d46 5 a50 1 -- SimpCon interface d52 5 a56 15 address : in std_logic_vector(addr_bits-1 downto 0); wr_data : in std_logic_vector(31 downto 0); rd, wr : in std_logic; rd_data : out std_logic_vector(31 downto 0); rdy_cnt : out unsigned(1 downto 0); -- interrupt irq : out std_logic; irq_ena : out std_logic; -- exception exc_req : in exception_type; exc_int : out std_logic; a79 34 component ac97_top is port ( clk_i : in std_logic; rst_i : in std_logic; -- WISHBONE SLAVE INTERFACE wb_data_i : in std_logic_vector(31 downto 0); wb_data_o : out std_logic_vector(31 downto 0); wb_addr_i : in std_logic_vector(31 downto 0); wb_sel_i : in std_logic_vector(3 downto 0); wb_we_i : in std_logic; wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_ack_o : out std_logic; wb_err_o : out std_logic ; -- Misc Signals int_o : out std_logic; dma_req_o : out std_logic_vector(8 downto 0); dma_ack_i : in std_logic_vector(8 downto 0); -- Suspend Resume Interface suspended_o : out std_logic; -- AC97 Codec Interface bit_clk_pad_i : in std_logic; sync_pad_o : out std_logic; sdata_pad_o : out std_logic; sdata_pad_i : in std_logic; ac97_reset_pad_o : out std_logic ); end component; d82 1 d100 1 d110 1 a110 1 sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS))); d113 2 a114 2 rd_data <= sc_dout(sel_reg); rdy_cnt <= sc_rdy_cnt(sel_reg); d117 1 a117 1 -- Connect SLAVE_CNT slaves d121 2 a122 2 sc_rd(i) <= rd when i=sel else '0'; sc_wr(i) <= wr when i=sel else '0'; d134 1 a134 1 if rd='1' then d148 2 a149 2 address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, d155 1 a155 3 irq => irq, irq_ena => irq_ena, a156 1 exc_int => exc_int, d174 2 a175 2 address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, d195 2 a196 2 address => address(SLAVE_ADDR_BITS-1 downto 0), wr_data => wr_data, a208 1 @