head	1.15;
access;
symbols
	bg2_23:1.13
	bg2_22:1.13
	bg2_21:1.13
	bg2_20:1.13
	bg2_16:1.13
	bg2_15:1.13
	bg2_12:1.12
	bg2_07:1.12
	isorc2008_submission:1.9
	handbook_alpha_edition:1.9
	jtres2007_submission:1.8
	bg1_07:1.7
	bg1_06:1.7
	bg1_05:1.7
	TAL_101:1.7
	TAL_100:1.7;
locks; strict;
comment	@# @;


1.15
date	2008.08.22.12.34.10;	author 9914pich;	state Exp;
branches;
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1.14
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1.13
date	2008.05.30.13.12.55;	author 9914pich;	state Exp;
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1.12
date	2008.02.23.23.18.46;	author martin;	state Exp;
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1.11
date	2008.02.20.14.29.32;	author martin;	state Exp;
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1.10
date	2008.01.09.13.44.57;	author 9914pich;	state Exp;
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1.9
date	2007.09.09.12.15.58;	author martin;	state Exp;
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1.8
date	2007.06.04.19.38.51;	author martin;	state Exp;
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1.7
date	2006.08.17.11.18.35;	author martin;	state Exp;
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1.6
date	2006.08.17.11.05.23;	author martin;	state Exp;
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1.5
date	2006.08.17.00.30.37;	author martin;	state Exp;
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1.4
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1.3
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1.2
date	2006.08.10.22.51.38;	author martin;	state Exp;
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1.1
date	2006.08.06.23.18.23;	author martin;	state Exp;
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desc
@@


1.15
log
@no message
@
text
@--
--
--  This file is a part of JOP, the Java Optimized Processor
--
--  Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com)
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--


--
--	sc_sram16.vhd
--
--	SimpCon compliant external memory interface
--	for 16-bit SRAM (e.g. Altera DE2 board)
--
--	High 16-bit word is at lower address
--
--	Connection between mem_sc and the external memory bus
--
--	memory mapping
--	
--		000000-x7ffff	external SRAM (w mirror)	max. 512 kW (4*4 MBit)
--
--	RAM: 16 bit word
--
--
--	2006-08-01	Adapted from sc_ram32.vhd
--	2006-08-16	Rebuilding the already working (lost) version
--				Use wait_state, din register without MUX
--	2007-06-04	changed SimpCon to records
--	2007-09-09	Additional input register for high data (correct SimpCon violation)
--	2008-05-29	nwe on pos edge, additional wait state for write
--

Library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

use work.jop_types.all;
use work.sc_pack.all;

entity sc_mem_if is
generic (ram_ws : integer; addr_bits : integer);

port (

	clk, reset	: in std_logic;

--
--	SimpCon memory interface
--
	sc_mem_out		: in sc_out_type;
	sc_mem_in		: out sc_in_type;

-- memory interface

	ram_addr	: out std_logic_vector(addr_bits-1 downto 0);
	ram_dout	: out std_logic_vector(15 downto 0);
	ram_din		: in std_logic_vector(15 downto 0);
	ram_dout_en	: out std_logic;
	ram_ncs		: out std_logic;
	ram_noe		: out std_logic;
	ram_nwe		: out std_logic

);
end sc_mem_if;

architecture rtl of sc_mem_if is

--
--	signals for mem interface
--
	type state_type		is (
							idl, rd1_h, rd2_h, rd1_l, rd2_l,
							wr1_h, wr2_h, wr_idl, wr1_l, wr2_l
						);
	signal state 		: state_type;
	signal next_state	: state_type;

	signal wait_state	: unsigned(3 downto 0);
	signal cnt			: unsigned(1 downto 0);

	signal dout_ena		: std_logic;
	signal rd_data_ena_h	: std_logic;
	signal rd_data_ena_l	: std_logic;
	signal inc_addr			: std_logic;
	signal wr_low			: std_logic;

	signal ram_dout_low		: std_logic_vector(15 downto 0);
	signal ram_din_high		: std_logic_vector(15 downto 0);

	signal ram_din_reg	: std_logic_vector(31 downto 0);
	
	signal ram_ws_wr	: integer;

begin

	ram_ws_wr <= ram_ws+1; -- additional wait state for SRAM
	ram_dout_en <= dout_ena;
	sc_mem_in.rdy_cnt <= cnt;

--
--	Register memory address, write data and read data
--
process(clk, reset)
begin
	if reset='1' then

		ram_addr <= (others => '0');
		ram_dout <= (others => '0');
		ram_dout_low <= (others => '0');

	elsif rising_edge(clk) then

		if sc_mem_out.rd='1' or sc_mem_out.wr='1' then
			ram_addr <= sc_mem_out.address(addr_bits-2 downto 0) & "0";
		end if;
		if inc_addr='1' then
			ram_addr(0) <= '1';
		end if;
		if sc_mem_out.wr='1' then
			ram_dout <= sc_mem_out.wr_data(31 downto 16);
			ram_dout_low <= sc_mem_out.wr_data(15 downto 0);
		end if;
		if wr_low='1' then
			ram_dout <= ram_dout_low;
		end if;
		-- use an addtional input register to adhire the SimpCon spec
		-- to not change rd_data untill the full new word is available
		-- results in input MUX at RAM data input
		if rd_data_ena_h='1' then
			ram_din_high <= ram_din;
		end if;
		if rd_data_ena_l='1' then
			-- move first word to higher half
			ram_din_reg(31 downto 16) <= ram_din_high;
			-- read second word
			ram_din_reg(15 downto 0) <= ram_din;
		end if;

	end if;
end process;

	sc_mem_in.rd_data <= ram_din_reg;


--
--	next state logic
--
process(state, sc_mem_out, wait_state)

begin

	next_state <= state;

	case state is

		when idl =>
			if sc_mem_out.rd='1' then
				if ram_ws=0 then
					-- then we omit state rd1!
					next_state <= rd2_h;
				else
					next_state <= rd1_h;
				end if;
			elsif sc_mem_out.wr='1' then
				next_state <= wr1_h;
			end if;

		-- the WS state
		when rd1_h =>
			if wait_state=2 then
				next_state <= rd2_h;
			end if;

		when rd2_h =>
			-- go to read low word
			if ram_ws=0 then
				-- then we omit state rd1!
				next_state <= rd2_l;
			else
				next_state <= rd1_l;
			end if;

		-- the WS state
		when rd1_l =>
			if wait_state=2 then
				next_state <= rd2_l;
			end if;

		-- last read state
		when rd2_l =>
			next_state <= idl;
			-- This should do to give us a pipeline
			-- level of 2 for read
			if sc_mem_out.rd='1' then
				if ram_ws=0 then
					-- then we omit state rd1!
					next_state <= rd2_h;
				else
					next_state <= rd1_h;
				end if;
			elsif sc_mem_out.wr='1' then
				next_state <= wr1_h;
			end if;
			
		-- WS state high word
		when wr1_h =>
			if wait_state=2 then
				next_state <= wr2_h;
			end if;
		
		-- last write state
		when wr2_h =>
			next_state <= wr_idl;
			
		when wr_idl =>
			next_state <= wr1_l;
		
		-- WS write state low word
		when wr1_l =>
			if wait_state=2 then
				next_state <= wr2_l;
			end if;
			
		-- last write state
		when wr2_l =>
			next_state <= idl;
			-- This should do to give us a pipeline
			-- level of 2 for read
			if sc_mem_out.rd='1' then
				if ram_ws=0 then
					-- then we omit state rd1!
					next_state <= rd2_h;
				else
					next_state <= rd1_h;
				end if;
			elsif sc_mem_out.wr='1' then
				next_state <= wr1_h;
			end if;

	end case;
				
end process;

--
--	state machine register
--	output register
--
process(clk, reset)

begin
	if (reset='1') then
		state <= idl;
		dout_ena <= '0';
		ram_ncs <= '1';
		ram_noe <= '1';
		rd_data_ena_h <= '0';
		rd_data_ena_l <= '0';
		inc_addr <= '0';
		wr_low <= '0';
		ram_nwe <= '1';
	elsif rising_edge(clk) then

		state <= next_state;
		dout_ena <= '0';
		ram_ncs <= '1';
		ram_noe <= '1';
		rd_data_ena_h <= '0';
		rd_data_ena_l <= '0';
		inc_addr <= '0';
		wr_low <= '0';
		ram_nwe <= '1';

		case next_state is

			when idl =>

			-- the wait state
			when rd1_h =>
				ram_ncs <= '0';
				ram_noe <= '0';

			-- high word last read state
			when rd2_h =>
				ram_ncs <= '0';
				ram_noe <= '0';
				rd_data_ena_h <= '1';
				inc_addr <= '1';
				
			-- the wait state
			when rd1_l =>
				ram_ncs <= '0';
				ram_noe <= '0';

			-- low word last read state
			when rd2_l =>
				ram_ncs <= '0';
				ram_noe <= '0';
				rd_data_ena_l <= '1';
				
			when wr1_h =>
				ram_nwe <= '0';
				dout_ena <= '1';
				ram_ncs <= '0';
			
			-- high word last write state	
			when wr2_h =>
				ram_ncs <= '0';

			when wr_idl =>
				ram_ncs <= '1';
				dout_ena <= '1';
				inc_addr <= '1';
				wr_low <= '1';

			when wr1_l =>
				ram_nwe <= '0';
				dout_ena <= '1';
				ram_ncs <= '0';
				
			when wr2_l =>
				ram_ncs <= '0';

		end case;
					
	end if;
end process;


--
-- wait_state processing
--
process(clk, reset)
begin
	if (reset='1') then
		wait_state <= (others => '1');
		cnt <= "00";
	elsif rising_edge(clk) then

		wait_state <= wait_state-1;

		cnt <= "11";
		if next_state=idl then
			cnt <= "00";
		end if;

		if sc_mem_out.rd='1' then
			wait_state <= to_unsigned(ram_ws+1, 4);
		end if;
		
		if sc_mem_out.wr='1' then
			wait_state <= to_unsigned(ram_ws_wr+1, 4);
		end if;

		if state=rd2_h then
			wait_state <= to_unsigned(ram_ws+1, 4);
			if ram_ws<3 then
				cnt <= to_unsigned(ram_ws+1, 2);
			else
				cnt <= "11";
			end if;
		end if;
			
		if state=wr_idl then
			wait_state <= to_unsigned(ram_ws_wr+1, 4);
			if ram_ws_wr<3 then
				cnt <= to_unsigned(ram_ws_wr+1, 2);
			else
				cnt <= "11";
			end if;
		end if;

		if state=rd1_l or state=rd2_l or state=wr1_l or state=wr2_l then
			-- take care for pipelined cach transfer
			-- there is no idl state and cnt should
			-- go back to "11"
			if sc_mem_out.rd='0' and sc_mem_out.wr='0' then
				-- if wait_state<4 then
				if wait_state(3 downto 2)="00" then
					cnt <= wait_state(1 downto 0)-1;
				end if;
			end if;
		end if;

	end if;
end process;

end rtl;
@


1.14
log
@fixed wait states are removed
@
text
@d87 1
a87 2
							wr1_h, wr2_h, wr3_h, wr_idl, 
							wr1_l, wr2_l, wr3_l
d219 1
a219 1
		-- first write state high word
a220 4
			next_state <= wr2_h;
		
		-- wait state
		when wr2_h =>
d222 1
a222 1
				next_state <= wr3_h;
d226 1
a226 1
		when wr3_h =>
d232 1
a232 1
		-- first write state low word
a233 4
			next_state <= wr2_l;
			
		-- wait state
		when wr2_l =>
d235 1
a235 1
				next_state <= wr3_l;
d239 1
a239 1
		when wr3_l =>
a314 3
				ram_ncs <= '0';
				
			when wr2_h =>
d320 1
a320 1
			when wr3_h =>
a329 3
				ram_ncs <= '0';
				
			when wr2_l =>
d334 1
a334 1
			when wr3_l =>
d386 1
a386 1
		if state=rd1_l or state=rd2_l or state=wr1_l or state=wr2_l or state=wr3_l then
@


1.13
log
@no message
@
text
@d220 1
d223 2
a224 1
			
d226 3
a228 1
			next_state <= wr3_h;
d230 1
d237 1
d241 1
d243 3
a245 1
			next_state <= wr3_l;
d247 1
d330 2
a331 1
				
a334 1
			-- high word last write state
@


1.12
log
@JOP goes GPL
@
text
@d44 1
d87 2
a88 1
							wr_h, wr_idl, wr_l
a92 1
	signal nwr_int		: std_logic;
d106 2
d111 1
a112 1

a158 14
--
--	'delay' nwe 1/2 cycle -> change on falling edge
--
process(clk, reset)

begin
	if (reset='1') then
		ram_nwe <= '1';
	elsif falling_edge(clk) then
		ram_nwe <= nwr_int;
	end if;

end process;

d180 1
a180 1
				next_state <= wr_h;
d217 1
a217 1
				next_state <= wr_h;
d220 9
a228 11
		-- the WS state
		when wr_h =>
-- TODO: check what happens on ram_ws=0
-- TODO: do we need a write pipelining?
--	not at the moment, but parhaps later when
--	we write the stack content to main memory
			if wait_state=1 then
				next_state <= wr_idl;
			end if;

		-- one idle state for nwr to go high
d230 21
a250 6
			next_state <= wr_l;

		-- the WS state
		when wr_l =>
			if wait_state=1 then
				next_state <= idl;
d273 1
d284 1
d313 1
a313 2
			-- the WS state
			when wr_h =>
d315 3
d319 4
d331 1
a331 2
			-- the WS state
			when wr_l =>
d333 3
d337 4
a346 21
--
--	nwr combinatorial processing
--	for the negativ edge
--
process(next_state, state)
begin

	nwr_int <= '1';
	-- this is the 'correct' version wich needs
	-- at minimum 2 cycles for the RAM access
--	if (state=wr_l and next_state=wr_l) or 
--		(state=wr_h and next_state=wr_h) then
	-- Slightly out of the SRAM spec. nwr goes
	-- low befor ncs to allow single cycle
	-- access
	if next_state=wr_l or next_state=wr_h then

		nwr_int <= '0';
	end if;

end process;
d365 1
a365 1
		if sc_mem_out.rd='1' or sc_mem_out.wr='1' then
d368 4
d373 1
a373 1
		if state=rd2_h or state=wr_idl then
d381 9
d391 1
a391 1
		if state=rd1_l or state=rd2_l or state=wr_l then
@


1.11
log
@Cleanup of SimpCon types
@
text
@d2 21
@


1.10
log
@no message
@
text
@d42 1
a42 1
	sc_mem_out		: in sc_mem_out_type;
@


1.9
log
@additional register at RAM input to correct SimpCon violation
@
text
@d153 1
a153 1
process(state, sc_mem_out.rd, sc_mem_out.wr, wait_state)
@


1.8
log
@records
@
text
@d22 1
d80 2
a81 2
	signal ram_dout_low	: std_logic_vector(15 downto 0);
	signal ram_din_low		: std_logic_vector(15 downto 0);
d117 3
d121 1
a121 1
			ram_din_reg(15 downto 0) <= ram_din;
d125 1
a125 1
			ram_din_reg(31 downto 16) <= ram_din_reg(15 downto 0);
@


1.7
log
@nwr goes low befor ncs to allow single cycle SRAM
@
text
@d21 1
d29 1
d38 5
a42 7
-- SimpCon interface

	address		: in std_logic_vector(addr_bits-1 downto 0);
	wr_data		: in std_logic_vector(31 downto 0);
	rd, wr		: in std_logic;
	rd_data		: out std_logic_vector(31 downto 0);
	rdy_cnt		: out unsigned(1 downto 0);
d88 1
a88 1
	rdy_cnt <= cnt;
d103 2
a104 2
		if rd='1' or wr='1' then
			ram_addr <= address(addr_bits-2 downto 0) & "0";
d109 3
a111 3
		if wr='1' then
			ram_dout <= wr_data(31 downto 16);
			ram_dout_low <= wr_data(15 downto 0);
d129 1
a129 1
	rd_data <= ram_din_reg;
d149 1
a149 1
process(state, rd, wr, wait_state)
d158 1
a158 1
			if rd='1' then
d165 1
a165 1
			elsif wr='1' then
d195 1
a195 1
			if rd='1' then
d202 1
a202 1
			elsif wr='1' then
d345 1
a345 1
		if rd='1' or wr='1' then
d362 1
a362 1
			if rd='0' and wr='0' then
@


1.6
log
@pipelined read, works with  single wait state. 0 wait state does not
generate a write signal
@
text
@a98 1
--		rd_data <= (others => '0');
a117 1
--			rd_data(31 downto 16) <= ram_din;
a123 1
--			rd_data(15 downto 0) <= ram_din;
d314 8
a321 2
	if (state=wr_l and next_state=wr_l) or 
		(state=wr_h and next_state=wr_h) then
@


1.5
log
@use cnt
@
text
@d198 10
a207 10
--			if rd='1' then
--				if ram_ws=0 then
--					-- then we omit state rd1!
--					next_state <= rd2_h;
--				else
--					next_state <= rd1_h;
--				end if;
--			elsif wr='1' then
--				next_state <= wr_h;
--			end if;
d348 5
a352 5
--			if ram_ws<3 then
--				cnt <= to_unsigned(ram_ws+1, 2);
--			else
--				cnt <= "11";
--			end if;
d356 8
a363 3
			-- if wait_state<4 then
			if wait_state(3 downto 2)="00" then
				cnt <= wait_state(1 downto 0)-1;
@


1.4
log
@din register without a MUX
@
text
@d19 2
a343 8
--			cnt <= "11";
		else
--			if state=rd1_l or state=rd2_l or state=wr_l then
--				-- if wait_state<4 then
--				if wait_state(3 downto 2)="00" then
--					cnt <= wait_state(1 downto 0)-1;
--				end if;
--			end if;
d355 6
@


1.3
log
@ok with wait_state (1.2 was also ok with fixed ws)
no din register, no cnt use
@
text
@d97 1
a97 1
		rd_data <= (others => '0');
d116 2
a117 2
--			ram_din_reg(15 downto 0) <= ram_din;
			rd_data(31 downto 16) <= ram_din;
d120 5
a124 5
--			-- move first word to higher half
--			ram_din_reg(31 downto 16) <= ram_din_reg(15 downto 0);
--			-- read second word
--			ram_din_reg(15 downto 0) <= ram_din;
			rd_data(15 downto 0) <= ram_din;
d130 1
a130 1
--	rd_data <= ram_din_reg;
@


1.2
log
@still not working (in the dynamic case)
@
text
@d5 1
a5 2
--	for 16-bit SRAM (e.g. Altera DE2 board or
--	half of Cycore).
a18 1
--	2006-08-08	Hardcoded 2 cycle memory interface
d61 2
a62 2
							idl, rd1_h, rd2_h, rd_idl, rd1_l, rd2_l,
							wr1_h, wr2_h, wr_idl, wr1_l, wr2_l
d97 1
a97 2
--		rd_data <= (others => '0');
--		ram_din_reg <= (others => '0');
d116 2
a117 2
			ram_din_reg(15 downto 0) <= ram_din;
--			rd_data(31 downto 16) <= ram_din;
d120 5
a124 5
			-- move first word to higher half
			ram_din_reg(31 downto 16) <= ram_din_reg(15 downto 0);
			-- read second word
			ram_din_reg(15 downto 0) <= ram_din;
--			rd_data(15 downto 0) <= ram_din;
d130 1
a130 1
	rd_data <= ram_din_reg;
d160 6
a165 1
				next_state <= rd1_h;
d167 1
a167 1
				next_state <= wr1_h;
d170 1
d172 3
a174 1
			next_state <= rd2_h;
d177 7
a183 4
			next_state <= rd_idl;

		when rd_idl =>
			next_state <= rd1_l;
d185 1
d187 3
a189 1
			next_state <= rd2_l;
d191 1
d194 12
d207 9
a215 5
		when wr1_h =>
			next_state <= wr2_h;

		when wr2_h =>
			next_state <= wr_idl;
d217 1
d219 1
a219 1
			next_state <= wr1_l;
d221 5
a225 5
		when wr1_l =>
			next_state <= wr2_l;

		when wr2_l =>
			next_state <= idl;
a246 2
		nwr_int <= '1';

a256 1
		nwr_int <= '1';
d267 1
d272 1
d274 1
a274 5
			when rd_idl =>
				ram_ncs <= '0';
				ram_noe <= '0';
				inc_addr <= '1';

d279 1
d285 2
a286 6
			when wr1_h =>
				ram_ncs <= '0';
				dout_ena <= '1';
				nwr_int <= '0';

			when wr2_h =>
d290 1
d297 2
a298 6
			when wr1_l =>
				ram_ncs <= '0';
				dout_ena <= '1';
				nwr_int <= '0';

			when wr2_l =>
d308 16
d329 1
d333 2
d340 22
@


1.1
log
@Altera DE2 board (16 bit SRAM)
@
text
@d5 2
a6 1
--	for 16-bit SRAM (e.g. Altera DE2 board)
d20 1
d63 2
a64 2
							idl, rd1_h, rd2_h, rd1_l, rd2_l,
							wr_h, wr_idl, wr_l
d82 1
d99 2
a100 1
		rd_data <= (others => '0');
d119 2
a120 1
			rd_data(31 downto 16) <= ram_din;
d123 5
a127 1
			rd_data(15 downto 0) <= ram_din;
d133 2
d163 1
a163 6
				if ram_ws=0 then
					-- then we omit state rd1!
					next_state <= rd2_h;
				else
					next_state <= rd1_h;
				end if;
d165 1
a165 1
				next_state <= wr_h;
a167 1
		-- the WS state
d169 1
a169 3
			if wait_state=2 then
				next_state <= rd2_h;
			end if;
d172 4
a175 7
			-- go to read low word
			if ram_ws=0 then
				-- then we omit state rd1!
				next_state <= rd2_l;
			else
				next_state <= rd1_l;
			end if;
a176 1
		-- the WS state
d178 1
a178 3
			if wait_state=2 then
				next_state <= rd2_l;
			end if;
a179 1
		-- last read state
a181 12
			-- This should do to give us a pipeline
			-- level of 2 for read
			if rd='1' then
				if ram_ws=0 then
					-- then we omit state rd1!
					next_state <= rd2_h;
				else
					next_state <= rd1_h;
				end if;
			elsif wr='1' then
				next_state <= wr_h;
			end if;
d183 5
a187 9
		-- the WS state
		when wr_h =>
-- TODO: check what happens on ram_ws=0
-- TODO: do we need a write pipelining?
--	not at the moment, but parhaps later when
--	we write the stack content to main memory
			if wait_state=1 then
				next_state <= wr_idl;
			end if;
a188 1
		-- one idle state for nwr to go high
d190 4
a193 1
			next_state <= wr_l;
d195 2
a196 5
		-- the WS state
		when wr_l =>
			if wait_state=1 then
				next_state <= idl;
			end if;
d218 2
d230 1
a240 1
			-- high word last read state
d245 4
d250 1
a250 2
				
			-- the wait state
a254 1
			-- low word last read state
d260 6
a265 2
			-- the WS state
			when wr_h =>
a268 1
			-- high word last write state
d270 1
a270 1
				ram_ncs <= '0';
d275 6
a280 2
			-- the WS state
			when wr_l =>
a289 14
--	nwr combinatorial processing
--	for the negativ edge
--
process(next_state, state)
begin

	nwr_int <= '1';
	if next_state=wr_l or next_state=wr_h then
		nwr_int <= '0';
	end if;

end process;

--
a294 1
		wait_state <= (others => '1');
a297 2
		wait_state <= wait_state-1;

a302 21
		if rd='1' or wr='1' then
			wait_state <= to_unsigned(ram_ws+1, 4);
			cnt <= "11";
		end if;

		if state=rd2_h or state=wr_idl then
			wait_state <= to_unsigned(ram_ws+1, 4);
			if ram_ws<3 then
				cnt <= to_unsigned(ram_ws+1, 2);
			else
				cnt <= "11";
			end if;
		end if;

		if state=rd1_l or state=rd2_l or state=wr_l then
			-- if wait_state<4 then
			if wait_state(3 downto 2)="00" then
				cnt <= wait_state(1 downto 0)-1;
			end if;
		end if;

@