head 1.3; access; symbols bg2_23:1.3 bg2_22:1.3 bg2_21:1.3 bg2_20:1.3 bg2_16:1.3 bg2_15:1.3 bg2_12:1.3 bg2_07:1.3 isorc2008_submission:1.2 handbook_alpha_edition:1.2 jtres2007_submission:1.2 bg1_07:1.2 bg1_06:1.2 bg1_05:1.2 TAL_101:1.2 TAL_100:1.2; locks; strict; comment @# @; 1.3 date 2008.02.23.23.18.42; author martin; state Exp; branches; next 1.2; commitid b7347c0a9b84567; 1.2 date 2006.08.07.00.05.23; author martin; state Exp; branches; next 1.1; commitid 4a5c44d683c04567; 1.1 date 2006.08.06.23.17.05; author martin; state Exp; branches; next ; commitid 326444d6786d4567; desc @@ 1.3 log @JOP goes GPL @ text @-- -- -- This file is a part of JOP, the Java Optimized Processor -- -- Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . -- -- as generated by the wizzard and added generic LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY pll IS generic (multiply_by : natural; divide_by : natural); PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END pll; ARCHITECTURE SYN OF pll IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; lpm_type : STRING; operation_mode : STRING; pll_type : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_fbin : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; port_enable0 : STRING; port_enable1 : STRING; port_extclk0 : STRING; port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; port_extclkena0 : STRING; port_extclkena1 : STRING; port_extclkena2 : STRING; port_extclkena3 : STRING; port_sclkout0 : STRING; port_sclkout1 : STRING ); PORT ( inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire4_bv(0 DOWNTO 0) <= "0"; sub_wire4 <= To_stdlogicvector(sub_wire4_bv); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; sub_wire2 <= inclk0; sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; altpll_component : altpll GENERIC MAP ( clk0_divide_by => divide_by, clk0_duty_cycle => 50, clk0_multiply_by => multiply_by, clk0_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 20000, -- 50 Mhz = 20000 ps intended_device_family => "Cyclone II", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "FAST", port_activeclock => "PORT_UNUSED", port_areset => "PORT_UNUSED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_UNUSED", port_pfdena => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_enable0 => "PORT_UNUSED", port_enable1 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", port_extclkena0 => "PORT_UNUSED", port_extclkena1 => "PORT_UNUSED", port_extclkena2 => "PORT_UNUSED", port_extclkena3 => "PORT_UNUSED", port_sclkout0 => "PORT_UNUSED", port_sclkout1 => "PORT_UNUSED" ) PORT MAP ( inclk => sub_wire3, clk => sub_wire0 ); END SYN; @ 1.2 log @Altera DE2 board (16 bit SRAM) @ text @d1 21 @ 1.1 log @Cyclone II PLL (for DE2 board) @ text @d10 1 a10 1 ENTITY cyc2_pll IS d17 1 a17 1 END cyc2_pll; d20 1 a20 1 ARCHITECTURE SYN OF cyc2_pll IS @