head	1.3;
access;
symbols
	thesis:1.2
	arelease:1.1.1.1
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.3
date	2005.05.11.17.05.38;	author martin;	state dead;
branches;
next	1.2;
commitid	282742823b604567;

1.2
date	2004.04.07.18.32.04;	author martin;	state Exp;
branches;
next	1.1;

1.1
date	2004.02.19.13.24.33;	author martin;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2004.02.19.13.24.33;	author martin;	state Exp;
branches;
next	;


desc
@@


1.3
log
@resync with current development
@
text
@FILES
{
	VHDL_FILE = ..\wizzard\pll.vhd;
	VHDL_FILE = ..\..\vhdl\io\fifo.vhd;
	VHDL_FILE = ..\..\vhdl\io\uart.vhd;
	VHDL_FILE = ..\..\vhdl\io\cnt.vhd;
	VHDL_FILE = ..\..\vhdl\io\iomin.vhd;
	VHDL_FILE = ..\..\vhdl\offtbl.vhd;
	VHDL_FILE = ..\..\vhdl\jtbl.vhd;
	VHDL_FILE = ..\..\vhdl\core\ajbc.vhd;
	VHDL_FILE = ..\..\vhdl\core\aram.vhd;
	VHDL_FILE = ..\..\vhdl\core\arom.vhd;
	VHDL_FILE = ..\..\vhdl\core\bcfetch.vhd;
	VHDL_FILE = ..\..\vhdl\core\core.vhd;
	VHDL_FILE = ..\..\vhdl\core\decode.vhd;
	VHDL_FILE = ..\..\vhdl\core\fetch.vhd;
	VHDL_FILE = ..\..\vhdl\core\mem32.vhd;
	VHDL_FILE = ..\..\vhdl\core\mul.vhd;
	VHDL_FILE = ..\..\vhdl\core\shift.vhd;
	VHDL_FILE = ..\..\vhdl\core\stack.vhd;
	VHDL_FILE = ..\..\vhdl\top\jopcyc.vhd;
	CDF_FILE = jop.cdf;
	VECTOR_WAVEFORM_FILE = jop.vwf;
}
COMPILER_SETTINGS_LIST
{
	COMPILER_SETTINGS = jop;
}
SIMULATOR_SETTINGS_LIST
{
	SIMULATOR_SETTINGS = jop;
}
SOFTWARE_SETTINGS_LIST
{
	SOFTWARE_SETTINGS = Debug;
	SOFTWARE_SETTINGS = Release;
}
@


1.2
log
@Tuning of bytecode and microcode fetch.
10 bits ROM instead of 8 bits plus bcftbl-table.
Jopa generates an additional generic VHDL
file for the microinstruction ROM (rom.vhd).
@
text
@@


1.1
log
@Initial revision
@
text
@a8 1
	VHDL_FILE = ..\..\vhdl\bcfetbl.vhd;
@


1.1.1.1
log
@initial cvs import.
@
text
@@