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	bg2_07:1.5
	isorc2008_submission:1.4
	handbook_alpha_edition:1.4
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	bg1_07:1.4
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	lctes2006_submission:1.2
	rtgc_isorc2006:1.2.0.4
	isorc2006:1.2.0.2
	rtgc_paper:1.2
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locks; strict;
comment	@;; @;


1.5
date	2008.02.23.23.41.05;	author martin;	state Exp;
branches;
next	1.4;
commitid	135e47c0af0e4567;

1.4
date	2006.08.11.14.32.56;	author martin;	state Exp;
branches;
next	1.3;
commitid	18b744dc95154567;

1.3
date	2006.08.07.19.35.08;	author martin;	state Exp;
branches;
next	1.2;
commitid	6a2644d795eb4567;

1.2
date	2004.09.13.08.33.00;	author martin;	state Exp;
branches;
next	1.1;

1.1
date	2004.02.19.13.21.06;	author martin;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2004.02.19.13.21.06;	author martin;	state Exp;
branches;
next	;


desc
@@


1.5
log
@JOP goes GPL
@
text
@//
//  This file is a part of JOP, the Java Optimized Processor
//
//  Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com)
//
//  This program is free software: you can redistribute it and/or modify
//  it under the terms of the GNU General Public License as published by
//  the Free Software Foundation, either version 3 of the License, or
//  (at your option) any later version.
//
//  This program is distributed in the hope that it will be useful,
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
//  GNU General Public License for more details.
//
//  You should have received a copy of the GNU General Public License
//  along with this program.  If not, see <http://www.gnu.org/licenses/>.
//

//
//	memser.asm
//
//		memory test, write memory content to serial line
//

//
//	io address
//
io_cnt		=	-128
io_wd		=	-125
io_status	=	-112
io_uart		=	-111

ua_rdrf		= 	2
ua_tdre		= 	1

//
//	first vars for start
//
	mp		?		// pointer to method struct (two words in cpool)
	cp		?		// pointer to constants
	heap	?		// start of heap

	extbc	?		// flag if bc load is neccessary

//
//	local vars
//
a			?
b			?
c			?


//
//	but starts with pc=0!!! (so init bc is not really necassary)
//
			nop
			nop
			ldi	127
			nop			// written in adr/read stage!
			stsp




loop_cnt	= 32768

loop:
			ldi 0
			stm	a

// ldi 1
// nop
// bnz rd_loop
// nop
// nop

			ldi	io_wd
			stmwa
			ldi	1
			stmwd
			wait
			wait
wr_loop:

sys_wr_mem:
			ldm	a
			stmwa				// write ext. mem address
			ldm a
			stmwd				// write ext. mem data
			wait
			wait

			ldm	a
			ldi	1
			add
			stm	a

			ldm	a
			ldi	loop_cnt
			xor
			nop
			bnz	wr_loop
			nop
			nop


			ldi 0
			stm	a

			ldi	io_wd
			stmwa
			ldi	0
			stmwd
			wait
			wait

rd_loop:


sys_rd_mem:
			ldm	a
			stmra
			wait
			wait
			ldmrd		 		// read ext. mem

			stm	b

ser0:
			ldi	io_status
			stmra
			ldi	ua_tdre
			wait
			wait
			ldmrd
			and
			nop
			bz	ser0			
			nop
			nop
			
			ldi	io_uart
			stmwa
			ldm	b
			stmwd
			wait
			wait


			ldm	a
			ldi	1
			add
			stm	a

			ldm	a
			ldi	loop_cnt
			xor
			nop
			bnz	rd_loop
			nop
			nop

			ldi	1
			nop
			bnz	loop
			nop
			nop
@


1.4
log
@removed old IO command
@
text
@d2 19
@


1.3
log
@adapted to memory mapped UART
@
text
@d92 2
a93 2
			ldi	io_outp
			stioa
d95 4
a98 1
			stiod
@


1.2
log
@inserted two nops at beginning.
@
text
@a5 11
//
//	io register
//
io_addr		=	0
io_data		=	1
mem_rd_addr	= 2		// st
mem_rd_data	= 2		// ld
mem_wr_addr	= 3		// st
mem_status	= 3		// ld
mem_wr_data	= 4		// st
mem_cancel	= 4		// ld
d10 4
a13 4
io_cnt		=	0
io_wd		=	3
io_status	=	4
io_uart		=	5
d59 2
a60 2
			ldi	io_outp
			stioa
d62 3
a64 1
			stiod
a71 1
			nop
d101 1
a101 2
			stmra				// read ext. mem, mem_bsy comes one cycle later
			nop
d110 1
a110 1
			stioa
d112 3
a114 1
			ldiod
d117 1
a117 1
			bz	ser0
d120 1
d122 1
a122 1
			stioa
d124 3
a126 1
			stiod
@


1.1
log
@Initial revision
@
text
@d49 2
@


1.1.1.1
log
@initial cvs import.
@
text
@@