head	1.6;
access;
symbols
	bg2_23:1.6
	bg2_22:1.6
	bg2_21:1.6
	bg2_20:1.6
	bg2_16:1.6
	bg2_15:1.6
	bg2_12:1.6
	bg2_07:1.6
	isorc2008_submission:1.5
	handbook_alpha_edition:1.5
	jtres2007_submission:1.5
	bg1_07:1.5
	bg1_06:1.5
	bg1_05:1.5
	TAL_101:1.5
	TAL_100:1.5
	jtres_submission:1.5
	wises06_submission:1.5
	lctes2006_submission:1.5
	rtgc_isorc2006:1.4.0.4
	isorc2006:1.4.0.2
	rtgc_paper:1.4
	bg1_00:1.4
	nohandle:1.4;
locks; strict;
comment	@;; @;


1.6
date	2008.02.23.23.41.05;	author martin;	state Exp;
branches;
next	1.5;
commitid	135e47c0af0e4567;

1.5
date	2006.01.11.16.17.27;	author martin;	state Exp;
branches;
next	1.4;
commitid	45a343c52f874567;

1.4
date	2005.05.30.17.14.31;	author martin;	state Exp;
branches;
next	1.3;
commitid	31f6429b49c44567;

1.3
date	2005.05.12.21.05.11;	author martin;	state Exp;
branches;
next	1.2;
commitid	6e0c4283c5034567;

1.2
date	2005.05.12.16.42.29;	author martin;	state Exp;
branches;
next	1.1;
commitid	2819428387704567;

1.1
date	2005.05.11.16.08.29;	author martin;	state Exp;
branches;
next	;
commitid	4cae42822df64567;


desc
@@


1.6
log
@JOP goes GPL
@
text
@//
//  This file is a part of JOP, the Java Optimized Processor
//
//  Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com)
//
//  This program is free software: you can redistribute it and/or modify
//  it under the terms of the GNU General Public License as published by
//  the Free Software Foundation, either version 3 of the License, or
//  (at your option) any later version.
//
//  This program is distributed in the hope that it will be useful,
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
//  GNU General Public License for more details.
//
//  You should have received a copy of the GNU General Public License
//  along with this program.  If not, see <http://www.gnu.org/licenses/>.
//

//
//	mem_wb_test.asm
//
//	test for simulation
//
//
//	'special' constant for a version number
//	gets written in RAM at position 64
//	update it when changing .asm, .inc or .vhdl files
//
version		= 20050220


			nop
			nop
			ldi	128
			nop			// written in adr/read stage!
			stsp		// someting strange in stack.vhd A->B !!!
			nop
			ldi	-1
			nop


			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop


			ldi	3
			stmra
			wait
			wait
			ldmrd
ldi 1
ldi 2
ldi 3


			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop

// test mem interface
//
			ldi 15

			// this sequence takes 6 cycles with ram_cnt=3
			stmra				// start read ext. mem
			wait				// one for fetch
			wait				// one for decode
			ldmrd		 		// read ext. mem

			ldi 7				// read addr.for back to back wr/rd
			ldi	32				// write data
			ldi	16				// write address

			// this sequence takes 6 cycles with ram_cnt=3
			stmwa				// write ext. mem address
			stmwd				// write ext. mem data
			wait
			wait

			stmra				// start read ext. mem
			wait				// one for fetch
			wait				// one for decode
			ldmrd		 		// read ext. mem

			pop
			pop



			nop
			nop
			nop

// test wishbone interface
// we use negativ addresses to access the wishbone devices
//

			ldi	-2
			stmra
			wait
			wait
			ldmrd
			ldi	-1
			stmra
			wait
			wait
			ldmrd


			nop
			nop

			pop
			pop


			ldi	16
			ldi	-1
			stmwa
			stmwd
			wait
			wait

			ldi	-1
			stmra
			wait
			wait
			ldmrd

			nop
			nop

			pop

			nop
			nop
			nop

			// back to back write
			ldi	33				// write data
			ldi	17				// write address

			ldi	32				// write data
			ldi	16				// write address

			// this sequence takes 6 cycles with ram_cnt=3
			stmwa				// write ext. mem address
			stmwd				// write ext. mem data
			wait
			wait

			stmwa				// write ext. mem address
			stmwd				// write ext. mem data
			wait
			wait


			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
			nop
@


1.5
log
@set stack pointer to 128 for sp_ov check
@
text
@d2 19
@


1.4
log
@JOP is now a Wishbone master!
@
text
@d16 1
a16 1
			ldi	127
@


1.3
log
@no message
@
text
@d89 17
d108 18
d128 3
@


1.2
log
@change mem32 to not generate a bsy on ram_cnt=2.
remove nops from mem rd/wr in jvm.asm (jvm_call.inc).
bsy is set onle cycle earlier with 'wr'.
@
text
@d39 3
@


1.1
log
@resync with current development
@
text
@d63 1
a72 1
			ldi 7
d80 47
@