head     1.1;
branch   1.1.1;
access   ;
symbols  vlsi:1.1.1.1 marta:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2002.02.09.13.48.46;  author marta;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2002.02.09.13.48.46;  author marta;  state Exp;
branches ;
next     ;


desc
@@



1.1
log
@Initial revision
@
text
@-- VHDL data flow description generated from `cbc_bop`
--		date : Sat Sep  1 20:13:41 2001


-- Entity Declaration

ENTITY cbc_bop IS
  PORT (
  active : in BIT;	-- active
  clk : in BIT;	-- clk
  cke : in BIT;	-- cke
  ikey_ready : in BIT;	-- ikey_ready
  key_ready : in BIT;	-- key_ready
  dt_ready : in BIT;	-- dt_ready
  finish : in BIT;	-- finish
  e : in BIT;	-- e
  first_dt : inout BIT;	-- first_dt
  e_mesin : out BIT;	-- e_mesin
  s_mesin : out BIT;	-- s_mesin
  s_gen_key : out BIT;	-- s_gen_key
  emp_buf : out BIT;	-- emp_buf
  cp_ready : out BIT;	-- cp_ready
  cke_b_mode : out BIT;	-- cke_b_mode
  en_in : out BIT;	-- en_in
  en_iv : out BIT;	-- en_iv
  en_rcbc : out BIT;	-- en_rcbc
  en_out : out BIT;	-- en_out
  sel1 : out bit_vector(1 DOWNTO 0) ;	-- sel1
  sel2 : out bit_vector(1 DOWNTO 0) ;	-- sel2
  sel3 : out bit_vector(1 DOWNTO 0) ;	-- sel3
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END cbc_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF cbc_bop IS
  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;	-- current_state
  SIGNAL aux85 : BIT;		-- aux85
  SIGNAL aux82 : BIT;		-- aux82
  SIGNAL aux74 : BIT;		-- aux74
  SIGNAL aux69 : BIT;		-- aux69
  SIGNAL aux63 : BIT;		-- aux63
  SIGNAL aux60 : BIT;		-- aux60
  SIGNAL aux59 : BIT;		-- aux59
  SIGNAL aux58 : BIT;		-- aux58
  SIGNAL aux57 : BIT;		-- aux57
  SIGNAL auxinit2 : BIT;		-- auxinit2
  SIGNAL aux77 : BIT;		-- aux77
  SIGNAL aux78 : BIT;		-- aux78

BEGIN
  aux78 <= (not (active) and ((cke and ikey_ready) or aux69));
  aux77 <= (not (current_state (2)) and not (active) and not (current_state
(0)) and not (current_state (1)) and current_state (3));
  auxinit2 <= (not (current_state (3)) and ((current_state (1) and not (finish)
and not (active) and current_state (0)) or aux74));
  aux57 <= (dt_ready and e);
  aux58 <= (not (active) and not ((not (key_ready) or first_dt)) and aux57);
  aux59 <= ((not (current_state (3)) and not (current_state (1)) and not
(current_state (0)) and current_state (2) and aux58) or (aux57
and aux77));
  aux60 <= (not (active) and current_state (2));
  aux63 <= (current_state (1) or current_state (0));
  aux69 <= not ((current_state (3) and not (current_state (1)) and not (current_state
(0)) and current_state (2)));
  aux74 <= (not (current_state (1)) and ((not (current_state (2)) and not
(active)) or (not (current_state (0)) and not (active) and key_ready
and dt_ready and first_dt)));
  aux82 <= (not (current_state (3)) and ((not (active) and not (current_state
(0)) and current_state (1)) or (aux60 and not ((not (current_state
(0)) and not ((key_ready and dt_ready)))))));
  aux85 <= (finish and not (current_state (3)) and current_state (1) and
current_state (0));
  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED ((not ((not (current_state (3)) or active)) and (not (current_state
(1)) or aux60) and not ((not (e) and (current_state (2) or current_state
(1)))) and (current_state (0) or (not (current_state (2)) and
aux57))) or (not (current_state (3)) and ((not (current_state
(2)) and not (active)) or (current_state (1) and not (active)
and current_state (0)) or (not (aux63) and aux58))));
  END BLOCK label0;
  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED ((not (current_state (3)) or (not (active) and (current_state
(1) or (current_state (2) and current_state (0))))) and (current_state
(3) or (current_state (1) and (aux60 or (not (finish) and not
(active) and current_state (0)))) or aux74));
  END BLOCK label1;
  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED (active or (current_state (1) and not ((not (current_state (2))
and current_state (0)))) or (not (current_state (0)) and current_state
(2) and not ((key_ready and dt_ready))) or (current_state (3)
and (current_state (2) xor current_state (0))));
  END BLOCK label2;
  label3 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (3) <= GUARDED (active or (current_state (2) and aux63) or aux85 or (not (current_state
(1)) and current_state (3) and (current_state (0) or (not (current_state
(2)) and not (dt_ready)) or (current_state (2) and not ((cke
and ikey_ready))))));
  END BLOCK label3;

sel3 (0) <= '0';

sel3 (1) <= (not (dt_ready) or active or e or (not (current_state (3)) and
not (current_state (2))) or aux63 or (current_state (2) and
(current_state (3) or not (key_ready) or first_dt)));

sel2 (0) <= aux59;

sel2 (1) <= not (aux59);

sel1 (0) <= ((aux60 and (current_state (1) or (not (e) and current_state
(0)))) or aux77 or aux82);

sel1 (1) <= ((not (current_state (3)) or active or (current_state (2) xor
aux63)) and not (aux82));

en_out <= (current_state (3) and not (active) and current_state (0) and
(not (current_state (1)) or current_state (2)));

en_rcbc <= (not (active) and aux85);

en_iv <= (not (active) and current_state (1) and (current_state (3) or
not ((not (current_state (2)) and current_state (0)))));

en_in <= auxinit2;

cke_b_mode <= (not (active) and cke and (ikey_ready or aux69));

cp_ready <= (not (active) and current_state (1) and not ((not (current_state
(3)) and not (current_state (2)))));

emp_buf <= auxinit2;

s_gen_key <= aux78;

s_mesin <= (not (active) and aux85);

e_mesin <= (e or not (aux78));

first_dt <= ((dt_ready and not (current_state (0)) and not (current_state
(1)) and current_state (3)) or not ((not (active) and not ((not
(current_state (1)) and not (current_state (0)) and current_state
(2))))));
END;
@


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