head     1.1;
branch   1.1.1;
access   ;
symbols  vlsi:1.1.1.1 marta:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2002.02.09.13.46.51;  author marta;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2002.02.09.13.46.51;  author marta;  state Exp;
branches ;
next     ;


desc
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1.1
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@Initial revision
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@-- VHDL data flow description generated from `adder01`
--		date : Mon Jul 30 22:16:40 2001


-- Entity Declaration

ENTITY adder01 IS
  PORT (
  a : in BIT;	-- a
  b : in BIT;	-- b
  cin : in BIT;	-- cin
  sum : out BIT;	-- sum
  cout : out BIT;	-- cout
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END adder01;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF adder01 IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on adder17x"
    SEVERITY WARNING;


cout <= ((a and b) or (cin and (a or b)));

sum <= (a xor b xor cin);
END;
@


1.1.1.1
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