head     1.1;
branch   1.1.1;
access   ;
symbols  vlsi:1.1.1.1 marta:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2002.02.09.13.48.32;  author marta;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2002.02.09.13.48.32;  author marta;  state Exp;
branches ;
next     ;


desc
@@



1.1
log
@Initial revision
@
text
@-- VHDL data flow description generated from `fulladder_bopo`
--		date : Sat Sep  8 00:29:32 2001


-- Entity Declaration

ENTITY fulladder_bopo IS
  PORT (
  a : in BIT;	-- a
  b : in BIT;	-- b
  cin : in BIT;	-- cin
  cout : out BIT;	-- cout
  sout : out BIT;	-- sout
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END fulladder_bopo;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF fulladder_bopo IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on fulladder"
    SEVERITY WARNING;


sout <= (a xor b xor cin);

cout <= ((a and b) or (cin and (a or b)));
END;
@


1.1.1.1
log
@no message
@
text
@@