head	1.1;
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	arelease:1.1.1.2
	avendor:1.1.1;
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1.1
date	2008.06.06.09.19.30;	author hmanske;	state Exp;
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	1.1.1.1;
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commitid	58624849010f4567;

1.1.1.1
date	2008.06.06.09.19.30;	author hmanske;	state Exp;
branches;
next	1.1.1.2;
commitid	58624849010f4567;

1.1.1.2
date	2008.06.06.10.27.06;	author hmanske;	state Exp;
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commitid	7895484910e74567;


desc
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1.1
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@Initial revision
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@------------------------------------------------------------------
-- PROJECT:     clvp (configurable lightweight vector processor)
--
-- ENTITY:      demultiplexer1x4
--
-- PURPOSE:     demultiplexer, one input, four outputs
--
-- AUTHOR:      harald manske, haraldmanske@@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity demultiplexer1x4 is
    port(   selector:       in std_logic_vector(1 downto 0);
            data_in:        in std_logic;
            data_out_00:    out std_logic;
            data_out_01:    out std_logic;
            data_out_10:    out std_logic;
            data_out_11:    out std_logic
         );
         
end demultiplexer1x4;

architecture rtl of demultiplexer1x4 is   
begin
   data_out_00 <= data_in when selector = "00" else '0';
   data_out_01 <= data_in when selector = "01" else '0';
   data_out_10 <= data_in when selector = "10" else '0';
   data_out_11 <= data_in when selector = "11" else '0';
end rtl;

@


1.1.1.1
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1.1.1.2
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@d2 1
a2 1
-- PROJECT:      HiCoVec (highly configurable vector processor)
@