head	1.2;
access;
symbols
	V10:1.1.1.1 GNU:1.1.1;
locks; strict;
comment	@# @;


1.2
date	2008.04.10.00.42.29;	author fisher5090;	state dead;
branches;
next	1.1;
commitid	6f2347fd62734567;

1.1
date	2006.05.31.05.59.39;	author fisher5090;	state Exp;
branches
	1.1.1.1;
next	;
commitid	256f447d30c94567;

1.1.1.1
date	2006.05.31.05.59.39;	author fisher5090;	state Exp;
branches;
next	;
commitid	256f447d30c94567;


desc
@@


1.2
log
@Replay xilinx fifo with private fifo
@
text
@# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\10G\ethmac10g
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\10G\ethmac10g
SET device = xc2vp20
# SET projectname = F:\10G\ethmac10g
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg676
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET memory_type=Block_Memory
CSET write_acknowledge_flag=false
CSET data_width=64
CSET write_error_flag=false
CSET read_acknowledge_sense=Active_Low
CSET data_count_width=8
CSET fifo_depth=128
CSET component_name=rxdatafifo
CSET data_count=false
CSET read_acknowledge_flag=false
CSET read_error_sense=Active_Low
CSET read_error_flag=false
CSET write_acknowledge_sense=Active_Low
CSET write_error_sense=Active_Low
# END Parameters
GENERATE


@


1.1
log
@Initial revision
@
text
@@


1.1.1.1
log
@first version
@
text
@@